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WM8960CGEFL/V Datasheet(PDF) 80 Page - Cirrus Logic |
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WM8960CGEFL/V Datasheet(HTML) 80 Page - Cirrus Logic |
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80 / 94 page ![]() WM8960 80 Rev 4.4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 6:5 00 Reserved 4 BUFDCOPEN 0 Enables the VGS / R current generator 0 = Disabled 1 = Enabled 3 BUFIOEN 0 Enables the VGS / R current generator and the analogue input and output bias 0 = Disabled 1 = Enabled 2 SOFT_ST 0 Enables VMID soft start 0 = Disabled 1 = Enabled 1 0 Reserved 0 HPSTBY 0 Headphone Amplifier Standby 0 = Standby mode disabled (Normal operation) 1 = Standby mode enabled R29 (1Dh) Anti-pop 2 8:7 00 Reserved 6 DISOP 0 Discharges the DC-blocking headphone capacitors on HP_L and HP_R 0 = Disabled 1 = Enabled 5:4 DRES[1:0] 00 DRES determines the value of the resistors used to discharge the DC-blocking headphone capacitors when DISOP=1 DRES[1:0] Resistance (Ohms) 0 0 400 0 1 200 1 0 600 1 1 150 3:0 0000 Reserved R30 (1Eh) 8:0 000000000 Reserved R31 (1Fh) 8:0 000000000 Reserved R32 (20h) ADCL Signal Path 8 LMN1 1 Connect LINPUT1 to inverting input of Left Input PGA 0 = LINPUT1 not connected to PGA 1 = LINPUT1 connected to PGA Input Signal Path 7 LMP3 0 Connect LINPUT3 to non-inverting input of Left Input PGA 0 = LINPUT3 not connected to PGA 1 = LINPUT3 connected to PGA (Constant input impedance) Input Signal Path 6 LMP2 0 Connect LINPUT2 to non-inverting input of Left Input PGA 0 = LINPUT2 not connected to PGA 1 = LINPUT2 connected to PGA (Constant input impedance) Input Signal Path 5:4 LMICBOOST[1:0] 00 Left Channel Input PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB Input Signal Path 3 LMIC2B 0 Connect Left Input PGA to Left Input Boost Mixer 0 = Not connected 1 = Connected Input Signal Path 2:0 000 Reserved |
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