WM8960CGEFLSLASHV datasheet(62/94 Pages) CIRRUS

62 / 94 page

WM8960

Rev 4.4

Although the ADC and DAC can run at different sample rates, they share the same bit clock pin

BCLK.

When operating in master mode, register bits BCLKDIV[3:0] should be set to an appropriate value to

ensure that there are sufficient BCLK cycles to transfer the complete data word from the ADCs and to

the DACs.

When operating in slave mode, the host device must provide sufficient BCLK cycles to transfer

complete data words to the ADCs and DACs.

Table 41 shows the maximum word lengths supported for a given SYSCLK and BCLKDIV, assuming

that either the ADCs or DACs are running at maximum rate (i.e. ADCDIV[2:0]=000 or

DACDIV[2:0]=000).

SYSCLK

(=MCLK OR PLL OUTPUT)

(MHz)

BCLKDIV[3:0]

BCLK RATE

(MASTER MODE)

(MHz)

MAXIMUM WORD LENGTH

(AT MAXIMUM ADC OR

DAC SAMPLE RATE)

12.288

0000 (=1)

12.288

0001 (=1.5)

8.192

0010 (=2)

6.144

0011 (=3)

4.096

0100 (=4)

3.072

0101 (=5.5)

2.2341818

0110 (=6)

2.048

0111 (=8)

1.536

1000 (=11)

1.117091

1001 (=12)

1.024

1010 (=16)

0.768

1011 (=22)

0.558545

N/A

1100 (=24)

0.512

N/A

1101 (=32)

0.384

N/A

1110 (=32)

0.384

N/A

1111 (=32)

0.384

N/A

11.2896

0000 (=1)

11.2896

0001 (=1.5)

7.5264

0010 (=2)

5.6448

0011 (=3)

3.7632

0100 (=4)

2.8224

0101 (=5.5)

2.052655

0110 (=6)

1.8816

0111 (=8)

1.4112

1000 (=11)

1.026327

1001 (=12)

0.9408

1010 (=16)

0.7056

1011 (=22)

0.513164

N/A

1100 (=24)

0.4704

N/A

1101 (=32)

0.3528

N/A

1110 (=32)

0.3528

N/A

1111 (=32)

0.3528

N/A

Table 41 BCLK Divider in Master Mode

WM8960CGEFL/V Datasheet(PDF) 62 Page - Cirrus Logic

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