WM8960CGEFLSLASHV datasheet(52/94 Pages) CIRRUS

52 / 94 page

WM8960

Rev 4.4

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 0

Figure 26 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles after each LRCLK transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 0

Figure 27 Right Justified Audio Interface (assuming n-bit word length)

In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

WM8960CGEFL/V Datasheet(PDF) 52 Page - Cirrus Logic

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