WM8960CGEFLSLASHV datasheet(14/94 Pages) CIRRUS

14 / 94 page

WM8960

Rev 4.4

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 2 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA = +25

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK cycle time

TMCLKY

33.33

MCLK duty cycle

TMCLKDS

60:40

40:60

AUDIO INTERFACE TIMING – MASTER MODE

BCLK

(Output)

ADCDAT

ADCLRC/

DACLRC

(Output)

DACDAT

DDA

DHT

DST

Figure 2 Digital Audio Data Timing

– Master Mode (see “Control Interface”)

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25

oC, Slave

Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

ADCLRC/DACLRC propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

MCLK

tMCLKY

WM8960CGEFL/V Datasheet(PDF) 14 Page - Cirrus Logic

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