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WM8960CGEFL/V Datasheet(PDF) 84 Page - Cirrus Logic |
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WM8960CGEFL/V Datasheet(HTML) 84 Page - Cirrus Logic |
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84 / 94 page ![]() WM8960 84 Rev 4.4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3:2 HPSEL[1:0] 00 Headphone Switch Input Select 0X = GPIO1 used for jack detect input (Requires ADCLRC pin to be configured as a GPIO) 10 = JD2 used for jack detect input 11 = JD3 used for jack detect input Headphone Jack Detect 1 TSENSEN 1 Temperature Sensor Enable 0 = Temperature sensor disabled 1 = Temperature sensor enabled Thermal Shutdown 0 MBSEL 0 Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Input Signal Path R49 (31h) Class D Control (1) 8 0 Reserved 7:6 SPK_OP_EN[1:0] 00 Enable Class D Speaker Outputs 00 = Off 01 = Left speaker only 10 = Right speaker only 11 = Left and right speakers enabled Enabling the Outputs 5:0 110111 Reserved R50 (32h) 8:0 001001101 Reserved R51 (33h) Class D Control (2) 8:6 010 Reserved 5:3 DCGAIN[2:0] 000 DC Speaker Boost (Boosts speaker DC output level by up to 1.8 x on left and right channels) 000 = 1.00x boost (+0dB) 001 = 1.27x boost (+2.1dB) 010 = 1.40x boost (+2.9dB) 011 = 1.52x boost (+3.6dB) 100 = 1.67x boost (+4.5dB) 101 = 1.8x boost (+5.1dB) 110 to 111 = Reserved Analogue Outputs 2:0 ACGAIN[2:0] 000 AC Speaker Boost (Boosts speaker AC output signal by up to 1.8 x on left and right channels) 000 = 1.00x boost (+0dB) 001 = 1.27x boost (+2.1dB) 010 = 1.40x boost (+2.9dB) 011 = 1.52x boost (+3.6dB) 100 = 1.67x boost (+4.5dB) 101 = 1.8x boost (+5.1dB) 110 to 111 = Reserved Analogue Outputs R52 (34h) PLL (1) 8:6 OPCLKDIV[2:0] 000 SYSCLK Output to GPIO Clock Division ratio 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 5.5 101 = SYSCLK / 6 General Purpose Input / Output 5 SDM 0 Enable Integer Mode 0 = Integer mode 1 = Fractional mode Clocking and Sample Rates 4 PLLPRESCALE 0 Divide MCLK by 2 before input to PLL 0 = Divide by 1 1 = Divide by 2 Clocking and Sample Rates |
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