EM78P372KSS20 datasheet(33/118 Pages) EMC

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EM78P372K

8-bit Microcontroller

Product Specification (V1.4) 05.11.2016

 25

(This specification is subject to change without prior notice)

7.2

Special Purpose Registers

7.2.1

A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the

temporary storage function of the Accumulator, which is not an addressable register.

7.2.2

CONT (Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTE

INT

PSTE

PST2

PST1

PST0

Note: The CONT register is both readable and writable.

Bit 6 is read only.

Bit 7 (INTE):

INT signal edge

0 : Interrupt occurs at a rising edge of the INT pin

1 : Interrupt occurs at a falling edge of the INT pin

Bit 6 (INT):

Interrupt Enable flag

0 : Masked by DISI or hardware interrupt

1 : Enabled by the ENI/RETI instructions

This bit is readable only.

Bit 5 (TS):

TCC signal source

0 : Internal instruction cycle clock. If P54 is used as I/O pin

1 : Transition on the TCC pin

Bit 4 (TE):

TCC signal edge

0 : Increment if the transition from low to high takes place on the

TCC pin

1 : Increment if the transition from high to low takes place on the

TCC pin.

Bit 3 (PSTE):

Prescaler enable bit for TCC

0 = prescaler disable bit. TCC rate is 1:1.

1 = prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0.

Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits

PST2

PST1

PST0

TCC Rate

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

EM78P372KSS20 Datasheet(PDF) 33 Page - ELAN Microelectronics Corp

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