MPF5023AMMA0ES datasheet(24/91 Pages) NXP

24 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

24 / 91

Table 19. Power down regulator group bits

OTP_SWx_PDGRP[1:0]

OTP_PGOOD_PDGRP[1:0]

OTP_RESETBMCU_PDGRP[1:0]

SWx_PDGRP[1:0]

PGOOD_PDGRP[1:0]

RESETBMCU_PDGRP[1:0]

Description

Regulator belongs to Group 4

Regulator belongs to Group 3

Regulator belongs to Group 2

Regulator belongs to Group 1

If PGOOD pin is used as a GPO, the PGOOD_PDGRP[1:0] is used to turn off the

PGOOD pin in a specific group during the power down sequence. If PGOOD pin is used

in power good mode, it is recommended that the OTP_PGOOD_PDGRP bits are set

to 11 to ensure the group power down sequencer does not detect these bits as part of

Group 4.

Each one of power down groups have programmable time delay registers to set the time

delay after the regulators in this group have been turned off, and the next group can start

to power down.

Table 20. Power down counter delay

OTP bits

OTP_GRPx_DLY[1:0]

Functional bits

GRPx_DLY[1:0]

Power down delay

(µs)

120

250

500

1000

If RESETBMCU is required to be asserted first before any of the external regulators from

the corresponding group, the RESETBMCU_DLY provides a selectable delay to disable

the regulators after RESETBMCU is asserted.

Table 21. Programmable delay after RESETBMCU is asserted

OTP bits

OTP_RESETBMCU_DLY[1:0]

Functional bits

RESETBMCU_DLY[1:0]

RESETBMCU delay

(µs)

No delay

100

500

If RESETBMCU_DLY is set to 0x00, all regulators in the same power down group as

RESETBMCU is disabled at the same time RESETBMCU is asserted.

Figure 10 shows an example of the power down sequence when PWRDWN_MODE = 1.

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