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MPF5023AMMA0ES Datasheet(PDF) 78 Page - NXP Semiconductors

Part # MPF5023AMMA0ES
Description  Power management integrated circuit (PMIC) for high performance applications
PDF  91 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF5023AMMA0ES Datasheet(HTML) 78 Page - NXP Semiconductors

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NXP Semiconductors
PF5023
Power management integrated circuit (PMIC) for high performance applications
PF5023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
78 / 91
ADDR
Register Name
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Configuration
A3
OTP CTRL3
0
0
0
0
0
0
0
1
VTT pull down enabled | Single phase: SW3 | Dual phase:
SW1/SW2
A4
OTP FREQ CTRL
0
0
0
0
0
0
0
0
SYNCIN = Disabled | SYNCOUT disabled | SYNCIN range
= 2 MHz to 3 MHz | CLK frequency = 2.5 MHz
A5
OTP PWRON
0
0
0
0
0
0
0
0
PWRON = Level sensitive
A6
OTP WD CONFIG
0
0
0
1
0
0
0
0
WDI generates soft WD Reset | WDI detect on rising edge
| WD timer disabled | WD timer in Standby disabled |WDI
detect in Standby disabled | WD Windows = 100 %
A7
OTP WD EXPIRE
0
0
0
0
0
1
1
1
Max WD Expire count = 8
A8
OTP WD COUNTER 1
0
1
0
1
1
1
1
WD Duration = 1024 ms | Max WD count = 16
A9
OTP FAULT
COUNTERS
1
1
1
1
1
1
1
1
Fail-safe MAX counter = 16 | Regulator Fault Max Counter
= 16
AA
OTP FAULT
TIMERS
0
0
0
0
1
1
1
1
Fail-safe OK timer = 1 minute | Regulator Fault timer =
Disabled
AB
OTP PWRDN DLY1 0
0
0
0
0
0
0
0
GRP4 delay = 125 µs | GRP 3 delay = 125 µs | GRP 2
delay = 125 µs | GRP 1 delay = 125 µs
AC
OTP PWRDN DLY2 0
0
0
0
0
0
0
1
Power Down Delay = 0 | RESETBMCU delay = 10 µs
AD
OTP PWRUP CTRL 0
0
0
0
0
0
1
0
PD Mirror Sequence | RESETBMCU PD Group2 | TBASE
= 250 µs
AE
OTP RESETBMCU
PWRUP
0
0
0
0
0
1
1
1
RESETBMCU SEQ = Slot 6 (TBASE x 6 = 1500 µs)
AF
OTP PGOOD
PWRUP
0
0
0
0
0
0
0
0
PGOOD SEQ = OFF
B0
OTP SW1 VOLT
0
1
1
0
0
0
0
0
Voltage = 1.0 V
B1
OTP SW1 PWRUP
0
0
0
0
0
0
0
1
SEQ = Slot 0
B2
OTP SW1 CONFIG1 0
1
0
1
0
0
1
1
UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min
3.1 A
B3
OTP SW1 CONFIG2 0
0
1
1
1
1
1
0
L = 1 µH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN
| WDBYPASS = Disable
B4
OTP SW2 VOLT
0
1
1
0
0
0
0
0
Voltage = 1.0 V
B5
OTP SW2 PWRUP
0
0
0
0
0
0
0
1
SEQ = Slot 0
B6
OTP SW2 CONFIG1 0
1
0
1
0
0
1
1
UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min
3.1 A
B7
OTP SW2 CONFIG2 0
0
0
1
1
1
1
0
L = 1 µH | Phase = 180º | DVS Ramp = 12.5 mV/µs | PG =
EN | WDBYPASS = Disabled
B8
OTP SW3_VOLT
0
1
1
1
0
0
0
0
Voltage = 1.1 V
B9
OTP SW3 PWRUP
0
0
0
0
0
1
0
1
SEQ = Slot 4 (TBASE x 4 = 1000 µs)
BA
OTP SW3 CONFIG1 0
1
0
1
0
0
1
1
UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min
3.1 A
BB
OTP SW3 CONFIG2 0
0
1
1
1
1
1
0
L = 1 µH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN
| WDBYPASS = Disable
BC
OTP SW4 VOLT
0
1
1
1
0
0
0
0
Voltage = 1.1 V
BD
OTP SW4 PWRUP
0
0
0
0
0
1
0
1
SEQ = Slot 4 (TBASE x 4 = 1000 µs)
BE
OTP SW4 CONFIG1 0
1
0
1
0
0
1
1
UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min
3.1 A
BF
OTP SW4 CONFIG2 0
0
1
1
1
1
1
0
L = 1 µH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN
| WDBYPASS = Disable
C8
OTP_OV_BYPASS1 0
0
0
0
0
0
0
0
SWx OVBYPASS disabled
CA
OTP_UV_BYPASS1 0
0
0
0
0
0
0
0
SWx UVBYPASS disabled
CC
OTP_ILIM_
BYPASS1
1
1
1
1
1
1
1
1
SWx ILIMBYPASS Enabled
CE
OTP_PROG_IDH
0
0
0
0
1
1
1
1
Default Program ID high Nibble = 0x0F
CF
OTP_PROF_IDL
1
1
1
1
1
1
1
1
Default Program ID low Byte = 0xFF



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