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MPF5023AMMA0ES Datasheet(PDF) 9 Page - NXP Semiconductors |
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MPF5023AMMA0ES Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 91 page  NXP Semiconductors PF5023 Power management integrated circuit (PMIC) for high performance applications PF5023 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 9 / 91 13 State machine The PF5023 features a state of the art state machine for seamless processor interface. The state machine handles the IC start up, provides fault monitoring and reporting, and protects the IC and the system during fault conditions. aaa-030044 Fault WD_Reset D Q O L R F K U J P M C E Z N S Fault POWER DOWN Turn-Off POWER DOWN 1. WD_FAIL_CNT = WD_MAX_CNT OR 2. PU_FAIL = True OR 3. FAULT_CNT = FAULT_MAX_CNT OR 4. Fault_Timer_Expired OR 5. Tj > TSD 1. PWRON = 0 OR 2. PWRON H to L && PWRON = 0 > TRESET OR 3. PMIC_OFF = 1 && 500 µs_Shutdown_timer_expired OR 4. VIN_OVLO_SDWN = 1 && VIN_OVLO detected Turn-off Power Up Sequence Off Modes WD Reset Event System ON Power up regulators per OTP sequence PU_FAIL = True Power up failure BG_OK OTP_OK 20 MHz_OK FS_CNT++ Regulators off Fail self-test (ST_COUNT < 3) FS_CNT = FS_MAX_CNT && OTP_FS_BYPASS = 0 1. FS_CNT < FS_MAX_CNT OR 2. OTP_FS_BYPASS = 1 Regulators off TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0 VIN > UVDET V1P5D_POR VIN < UVDET CRITICAL FAILURE WD_FAIL_CNT++ RESETBMCU = HIGH Sys ON Sequence RUN Fau lt Sh utdo wn Fa il s elf- tes ts (ST _C OU NT = 3 ) Tu rn- off ev en t Standby B A QPU_Off LP_Off Self- Test 2 ms delay OTP & Trim Load Fail-Safe State Fail-Safe Transition Power Down NO POWER PF502x ASILB only Legend PF502x QM only Figure 5. State diagram Table 10 lists the conditions for the different state machine transitions. |
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