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MPF5023AMMA0ES Datasheet(PDF) 32 Page - NXP Semiconductors |
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MPF5023AMMA0ES Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 91 page ![]() NXP Semiconductors PF5023 Power management integrated circuit (PMIC) for high performance applications PF5023 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 32 / 91 If the faulty condition is not cleared within the 2.0 ms timer, the power up sequence is aborted and the PF5023 turns off all voltage regulators enabled so far as shown in Figure 16. aaa-032240 Reg Power down 2 ms (max) Recovery RESETBMCU PGOOD3 PGOOD2 SW3 SW2 PGOOD1 SW1 PGOOD (optional) Figure 16. Power up sequencer aborted as fault persists for longer than 2.0 ms Supplies enabled after RESETBMCU are checked for OV, UV and ILIM faults after each of them are enabled. If an OV, UV or ILIM condition is present, the PF5023 starts a fault detection and protection mechanism as described in Section 14.7 "Fault detection". At this point, the MCU should be able to read the interrupt and react upon a fault event as defined by the system. If a regulator fault occurs after RESETBMCU is de-asserted but before the power up sequence is finalized, the power up sequences continue to turn on the remaining regulators as configured, even if a fault detection mechanism is active on an earlier regulator. 14.8 Interrupt management The MCU is notified of any interrupt through the INTB pin and various interrupt registers. The interrupt registers are composed by three types of bits to help manage all the interrupt requests in the PF5023: • The interrupt latch XXXX_I: this bit is set when the corresponding interrupt event occurs. It can be read at any time, and is cleared by writing a 1 to the bit. • The mask bit XXXX_M: this bit controls whether a given interrupt latch pulls the INTB pin low or not. • When the mask bit is 1, the interrupt latch does not control the INTB pin. • When the mask bit is 0, the INTB pin is pulled low as long as the corresponding latch bit is set. • The sense bit XXXX_S: if available, the sense bit provides the actual status of the signal triggering the interrupt. |
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