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MPF5023AMMA0ES Datasheet(PDF) 52 Page - NXP Semiconductors |
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MPF5023AMMA0ES Datasheet(HTML) 52 Page - NXP Semiconductors |
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52 / 91 page  NXP Semiconductors PF5023 Power management integrated circuit (PMIC) for high performance applications PF5023 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 52 / 91 Table 44. Recommended external components Symbol Parameter Min Typ Max Unit L Output inductor Maximum inductor DC resistance 50 mΩ Minimum saturation current at full load: 3.0 A [1] 0.47 1.0 1.5 µH Cout Output capacitor Use 2 × 22 µF, 6.3 V X7T ceramic capacitor to reduce output capacitance ESR 35 44 53 µF Cin Input capacitor 4.7 μF, 10 V X7R ceramic capacitor 4.23 4.7 5.17 µF [1] Keep inductor DCR as low as possible to improve regulator efficiency. 15.3 Voltage monitoring The PF5023 provides OV and UV monitoring capability for the following voltage regulators: • SW1, SW2, SW3 A programmable UV threshold is selected via the OTP_SWxUV_TH[1:0]. UV threshold selection represents a percentage of the nominal voltage programmed on each regulator. Table 45. UV threshold configuration register OTP_SWxUV_TH[1:0] UV threshold level 00 95 % 01 93 % 10 91 % 11 89 % A programmable OV threshold is selected via the OTP_SWxOV_TH[1:0]. OV threshold selection represents a percentage of the nominal voltage programmed on each regulator. Table 46. OV threshold configuration register OTP_SWxOV_TH OV threshold level 00 105 % 01 107 % 10 109 % 11 111 % Two functional bits are provided to program the UV debounce time for the voltage regulators. Table 47. UV debounce timer configuration UV_DB[1:0] UV debounce time 00 5 µs 01 15 µs 10 30 µs 11 40 µs The default value of the UV_DB[1:0] upon a full register reset is 0b10. Two functional bits to program the OV debounce time for all the voltage regulators. |
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