MPF5023AMMA0ES datasheet(91/91 Pages) NXP

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 April 2020

Document identifier: PF5023

Contents

Overview .............................................................. 1

Features ............................................................... 1

Simplified application diagram .......................... 2

Ordering information .......................................... 2

Applications .........................................................3

Internal block diagram ........................................3

Pinning information ............................................ 4

7.1

Pinning ...............................................................4

7.2

Pin description ................................................... 4

Absolute maximum ratings ................................5

ESD ratings ..........................................................5

Thermal characteristics ......................................6

Operating conditions ..........................................6

General description ............................................ 6

12.1

Features .............................................................6

12.2

Functional block diagram ...................................7

12.3

Power tree summary ......................................... 7

12.4

Device differences ............................................. 8

State machine ......................................................9

13.1

State descriptions ............................................ 12

13.1.1

OTP/TRIM load ................................................12

13.1.2

LP_Off state .....................................................12

13.1.3

Self-test routine (PF5023 ASIL B only) ............12

13.1.4

QPU_Off state ................................................. 13

13.1.5

Power up sequence .........................................13

13.1.6

System On state ..............................................13

13.1.6.1 Run state ......................................................... 14

13.1.6.2 Standby state ...................................................14

13.1.7

WD_Reset ........................................................15

13.1.8

Power down state ............................................15

13.1.9

Fail-safe transition ........................................... 15

13.1.10 Fail-safe state (PF5023 ASIL B only) .............. 16

General device operation ................................. 17

14.1

UVDET .............................................................17

14.2

VIN OVLO condition ........................................ 17

14.3

IC startup timing with PWRON pulled up ......... 18

14.4

IC startup timing with PWRON pulled low

during VIN application ..................................... 19

14.5

Power up ......................................................... 20

14.5.1

Power up events ..............................................20

14.5.2

Power up sequencing ......................................20

14.6

Power down .....................................................22

14.6.1

Turn off events ................................................ 22

14.6.2

Power down sequencing ................................. 23

14.6.2.1 Sequential power down ................................... 23

14.6.2.2 Group power down .......................................... 23

14.6.2.3 Power down delay ........................................... 25

14.7

Fault detection ................................................. 26

14.7.1

Fault monitoring during power up state ............30

14.8

Interrupt management ..................................... 32

14.9

I/O interface pins ............................................. 34

14.9.1

PWRON ........................................................... 35

14.9.2

STANDBY ........................................................36

14.9.3

RESETBMCU .................................................. 36

14.9.4

INTB .................................................................37

14.9.5

WDI ..................................................................37

14.9.6

PGOOD ............................................................38

14.9.7

PGOODx ..........................................................39

14.9.8

ENx .................................................................. 39

14.9.9

TBBEN .............................................................39

14.9.10 XFAILB .............................................................40

14.9.11 SDA and SCL (I2C bus) ..................................43

14.9.11.1 I2C CRC verification ........................................43

14.9.11.2 I2C secure write .............................................. 44

Functional blocks ..............................................45

15.1

Analog core and internal voltage references ....45

15.2

Type 1 buck regulators (SWx) .........................45

15.2.1

SW2 VTT operation .........................................48

15.2.2

Multiphase operation ....................................... 49

15.2.3

Electrical characteristics .................................. 49

15.3

Voltage monitoring ...........................................52

15.3.1

Electrical characteristics .................................. 54

15.4

Clock management ..........................................55

15.4.1

Low frequency clock ........................................56

15.4.2

High frequency clock ....................................... 56

15.4.3

Manual frequency tuning ................................. 56

15.4.4

Spread-spectrum ............................................. 57

15.4.5

Clock synchronization ......................................58

15.5

Thermal monitoring ..........................................60

15.6

Analog multiplexer ........................................... 62

15.7

Watchdog event management .........................62

15.7.1

Internal watchdog timer ................................... 62

15.7.2

Watchdog reset behaviors ...............................65

I2C register map ................................................68

16.1

PF5023 OTP mirror register map .................... 69

16.2

PF5023 functional register map .......................71

OTP/TBB

and

hardwire

default

configurations ................................................... 73

17.1

TBB (Try Before Buy) operation ...................... 74

17.2

OTP fuse programming ................................... 75

17.3

Default hardwire configuration .........................76

Functional safety ...............................................79

18.1

System safety strategy .................................... 79

18.2

Output voltage monitoring with dedicated

bandgap reference ...........................................79

18.3

ABIST verification ............................................ 80

IC level quiescent current requirements .........80

Typical applications ..........................................81

Package outline .................................................82

Revision history ................................................ 86

Legal information ..............................................87

MPF5023AMMA0ES Datasheet(PDF) 91 Page - NXP Semiconductors

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