MPF5023AMMA0ES datasheet(56/91 Pages) NXP

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

56 / 91

15.4.1 Low frequency clock

A low power 100 kHz clock is provided for overall logic and digital control. Internal logic

and debounce timers are based on this 100 kHz clock.

15.4.2 High frequency clock

The PF5023 features a high frequency clock with nominal frequency of 20 MHz. Clock

frequency is programmable over a range of ±20 % via the CLK_FREQ[3:0] control bits.

15.4.3 Manual frequency tuning

The PF5023 features a manual frequency tuning to set the switching frequency of the

high frequency clock. The CLK_FREQ [3:0] bits allow a manual frequency tuning of the

high frequency clock from 16 MHz to 24 MHz.

If a frequency change of two or more steps is requested by a single I2C command, the

device performs a gradual frequency change passing through all steps in between with a

5.2 µs time between each frequency step. When the frequency reaches the programmed

value, The FREQ_RDY_I asserts the INTB pin, provided it is not masked.

When the internal clock is used as the main frequency for the power generation, an

internal frequency divider by 8 is used to generate the switching frequency for all the

buck regulators. Adjusting the frequency of the high frequency clock allows for manual

tuning of the switching frequencies for the buck regulators from 2.0 MHz to 3.0 MHz.

Table 50. Manual frequency tuning configuration

CLK_FREQ[3:0]

High speed clock frequency

(MHz)

Switching regulators frequency

(MHz)

0000

2.500

0001

2.625

0010

2.750

0011

2.875

0100

3.000

0101

Not used

0110

Not used

0111

Not used

1000

Not used

1001

2.000

1010

2.125

1011

2.250

1100

2.375

1101

Not used

1110

Not used

1111

Not used

The default switching frequency is set by the OTP_CLK_FREQ[3:0] bits.

Manual tuning cannot be applied when frequency spread-spectrum or external

clock synchronization is used. However, during external clock synchronization, it is

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