MPF5023AMMA0ES datasheet(40/91 Pages) NXP

40 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

40 / 91

Disabling the watchdog operation may be required for in-line MCU programming where

output voltages are required but watchdog operation should be completely disabled.

14.9.10 XFAILB

XFAILB is a bidirectional pin with an open drain output used to synchronize the power

up and power down sequences of two or more PMICs. It should normally be pulled up

externally to V1P5A supply.

The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation.

• When OTP_XFAILB_EN = 0, the XFAILB mode is disabled and any events on this pin

are ignored.

• When OTP_XFAILB_EN = 1, the XFAILB mode is enabled

When the XFAILB mode is enabled, and the PF5023 has a turn off event generated by

an internal fault, the XFAILB pin is asserted low 20 µs before starting the power down

sequence.

A power down event caused by the following conditions will assert the XFAILB pin:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT (Regulator fault counter max out)

• WD_EVENT_CNT = WD_MAX_CNT (Watchdog event counter max out)

• Power up failure

• Thermal shutdown

• Hard WD event

The XFAILB pin is forced low during the Off mode.

During the system On state, if the XFAILB pin is externally pulled low, it will detect an

XFAIL event after a 20 µs debounce. When an XFAIL event is detected, the XFAILB pin

is asserted low internally and the device starts a power down sequence.

If a PWRON event is present, the device will start a turn on event and proceed to release

the XFAILB pin when its ready to start the power up sequence state. If the XFAILB pin

is pulled down externally during the power up event, the PF5023 will stop the power up

sequence until the pin is no longer pulled down externally. This will help both PMICs to

synchronize the power up sequence allowing it to continue only when both PMICs are

ready to initiate the power up sequence.

A hard WD event will set the XFAILB pin 20 µs before it starts its power down sequence.

After all regulator outputs have been turned off, the device will release the XFAILB pin

internally after a 30 µs delay, proceed to load the default OTP configuration and wait for

the XFAILB pin to be released externally before it can restart the power up sequence.

MPF5023AMMA0ES Datasheet(PDF) 40 Page - NXP Semiconductors

MPF5023AMMA0ES Datasheet(HTML) 40 Page - NXP Semiconductors

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