IMX7ULPIECB2 datasheet(49/112 Pages) NXP

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• Settling time of < 100 μsec

• RMS TIE jitter (long-term jitter) < 100 psec

• Frequency update must be smooth with no glitches

7.3 Power sequencing—system

7.3.1 Power-on sequencing

The power-on sequencing requirements for the device are described in this section.

VDD_VBAT42 must be powered and stable before all other supplies begin to ramp

up.

The real-time domain supplies must be powered and stable before RESET0_B is

deasserted. The real-time domain supplies listed below may be powered on in any

order except for those indicating specific sequencing requirements.

• VDD_PMC18_DIG0 and VDD_PMC18 must be powered on together, or

VDD_PMC18 must be powered on first followed by VDD_PMC18_DIG0

• VDD_PLL_18

• VDD_PTA

• VDD_PTB

• VDD18_IOREF

• VREFH_ANA18

• VREFL_ANA

• VDD_ANA18

• VDD_ANA33

The application domain supplies must be powered on and stable before the A7 core

exits reset. The M4 core controls the release of the A7 from reset. The application

domain supplies listed below may be powered on in any order except for those

indicating specific sequencing requirements.

• VDD_PMC12_DIG1

• VDD_PMC11_DIG1_CAP (if using A7 LDO bypass mode)

• VDD_DIG1 (if using A7 LDO bypass mode)

• VDD_PTC

• VDD_PTD and VDD18_IOREF must be powered together, or VDD18_IOREF

powered on first followed by VDD_PTD

• VDD_PTE

System specifications

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

IMX7ULPIECB2 Datasheet(PDF) 49 Page - NXP Semiconductors