SLG46867MTR datasheet(4/209 Pages) RENESAS

4 / 209 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 3.21

Page 4 of 208

SLG46867

GreenPAK Programmable Mixed-Signal Matrix

with Dual 44 m

Ω/2 A P-FET

Figures

Figure 1: Block Diagram............................................................................................................................................................. 8

Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................31

Figure 3: IO0 GPI Structure Diagram .......................................................................................................................................33

Figure 4: GPIO with I2C Mode IO Structure Diagram...............................................................................................................34

Figure 5: Matrix OE IO Structure Diagram ...............................................................................................................................35

Figure 6: Matrix OE IO 4x Drive Structure Diagram .................................................................................................................36

Figure 7: GPO Register OE 4x Drive Structure Diagram .........................................................................................................37

Figure 8: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C .......................................................38

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range ......................38

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .......................................39

Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range ....................39

Figure 12: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .......................................40

Figure 13: Connection Matrix ...................................................................................................................................................41

Figure 14: Connection Matrix Example ....................................................................................................................................41

Figure 15: 2-bit LUT0 or DFF0 .................................................................................................................................................48

Figure 16: 2-bit LUT1 or DFF1 .................................................................................................................................................49

Figure 17: 2-bit LUT2 or DFF2 .................................................................................................................................................49

Figure 18: DFF Polarity Operations..........................................................................................................................................51

Figure 19: 2-bit LUT3 or PGen .................................................................................................................................................52

Figure 20: PGen Timing Diagram.............................................................................................................................................52

Figure 21: 3-bit LUT0 or DFF3 .................................................................................................................................................54

Figure 22: 3-bit LUT1 or DFF4 .................................................................................................................................................55

Figure 23: 3-bit LUT2 or DFF5 .................................................................................................................................................55

Figure 24: 3-bit LUT3 or DFF6 .................................................................................................................................................56

Figure 25: 3-bit LUT4 or DFF7 .................................................................................................................................................56

Figure 26: 3-bit LUT5 or DFF8 .................................................................................................................................................57

Figure 27: 3-bit LUT6 or DFF9 .................................................................................................................................................57

Figure 28: 3-bit LUT7 or DFF10 ...............................................................................................................................................58

Figure 29: 3-bit LUT8 or DFF11 ...............................................................................................................................................58

Figure 30: DFF Polarity Operations with nReset......................................................................................................................61

Figure 31: DFF Polarity Operations with nSet..........................................................................................................................62

Figure 32: 4-bit LUT0 or DFF12 ...............................................................................................................................................63

Figure 33: 3-bit LUT16/Pipe Delay/Ripple Counter ..................................................................................................................65

Figure 34: Example: Ripple Counter Functionality ...................................................................................................................66

Figure 35: Possible Connections Inside Multi-Function Macrocell ...........................................................................................68

Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY1) ...................................................69

Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY2) .................................................70

Figure 38: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY3) .................................................71

Figure 39: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY4) .................................................72

Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF17, CNT/DLY5) .................................................73

Figure 41: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT14/DFF18, CNT/DLY6) .................................................74

Figure 42: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT15/DFF19, CNT/DLY7) .................................................75

Figure 43: 4-bit LUT1 or CNT/DLY0.........................................................................................................................................78

Figure 44: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ........................................................................80

Figure 45: Delay Mode Timing Diagram for Different Edge Select Modes...............................................................................81

Figure 46: Counter Mode Timing Diagram without Two DFFs Synced Up ..............................................................................81

Figure 47: Counter Mode Timing Diagram with Two DFFs Synced Up ...................................................................................82

Figure 48: One-Shot Function Timing Diagram........................................................................................................................82

Figure 49: Frequency Detection Mode Timing Diagram...........................................................................................................83

Figure 50: Edge Detection Mode Timing Diagram ...................................................................................................................84

Figure 51: Delayed Edge Detection Mode Timing Diagram .....................................................................................................85

Figure 52: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced on, UP = 0) for Counter Data = 3 ......86

Figure 53: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced on, UP = 0) for Counter Data = 3 ..........86

Figure 54: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced on, UP = 1) for Counter Data = 3 ......87

Figure 55: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 .........87

SLG46867MTR Datasheet(PDF) 4 Page - Renesas Technology Corp

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