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SLG46867MTR Datasheet(PDF) 91 Page - Renesas Technology Corp |
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SLG46867MTR Datasheet(HTML) 91 Page - Renesas Technology Corp |
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91 / 209 page ![]() Datasheet 28-Feb-2023 CFR0011-120-00 Revision 3.21 Page 91 of 208 © 2023 Renesas Electronics Corporation SLG46867 GreenPAK Programmable Mixed-Signal Matrix with Dual 44 m Ω/2 A P-FET Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.62 ms. The BG/analog start up time will take maximal 2.62 ms. Therefore, 8 periods of the Oscillator0 is recommended for the wake time, when BG is configured to Auto Power mode. If low power BG is always on, Oscillator0 period is longer than required wake time. The BG/analog start up time will Figure 60: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used Figure 61: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used Normal ACMP Operation ACMP follows input Sleep Mode ACMP Latches New Data Data is latched BG/Analog Startup time* Force Sleep Sleep Mode ACMP Latches Last Data BG/Analog_Good (internal signal) ACMP_PD is High (From Connection Matrix) CNT_SET (From Connection Matrix) CNT0_out (To Connection Matrix) time between Reset goes low and 1st WS clock rising edge WS_out (internal signal) Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH. Sleep Mode ACMP Latches New Data Data is latched BG/Analog Startup time* Normal ACMP Operation for short time ACMP follows input Force Sleep Sleep Mode ACMP Latches Last Data BG/Analog_Good (internal signal) ACMP_PD is High (From Connection Matrix) CNT_RST (From Connection Matrix) CNT0_out (To Connection Matrix) time between Reset goes low and 1st WS clock rising edge WS_out (internal signal) Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH. |
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