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SLG46867MTR Datasheet(PDF) 46 Page - Renesas Technology Corp

Part # SLG46867MTR
Description  GreenPAK Programmable Mixed-Signal Matrix with Dual 44 mW/2 A P-FET
PDF  209 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SLG46867MTR Datasheet(HTML) 46 Page - Renesas Technology Corp

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Datasheet
28-Feb-2023
CFR0011-120-00
Revision 3.21
Page 46 of 208
© 2023 Renesas Electronics Corporation
SLG46867
GreenPAK Programmable Mixed-Signal Matrix
with Dual 44 m
Ω/2 A P-FET
[419:414]
GPIO7 Digital Output
69
[425:420]
GPIO7 Output Enable
70
[431:426]
GPIO8 Digital Output
71
[437:432]
GPIO8 Output Enable
72
[443:438]
GPIO9 Digital Output
73
[449:444]
GPIO9 Output Enable
74
[455:450]
PWR UP of ACMP0H
75
[461:456]
PWR UP of ACMP1H
76
[467:462]
PWR UP of ACMP2L
77
[473:468]
PWR UP of ACMP3L
78
[479:474]
Temp sensor, Vref Out_0, Vref Out_1 Power Up
79
[485:480]
Oscillator0 ENABLE
80
[491:486]
Oscillator1 ENABLE
81
[497:492]
Oscillator2 ENABLE
82
[503:498]
IN0 of LUT4_1 or CLK Input of DFF20
Delay0 Input (or Counter0 nRST Input)
83
[509:504]
IN1 of LUT4_1 or nRST of DFF20
Delay0 Input (or Counter0 nRST Input)
84
[515:510]
IN2 of LUT4_1 or nSET of DFF20
Delay0 Input (or Counter0 nRST Input)
85
[521:516]
IN3 of LUT4_1 or Data of DFF20
Delay0 Input (or Counter0 nRST Input)
86
[527:522]
IN0 of LUT3_9 or CLK Input of DFF13
Delay1 Input (or Counter1 nRST Input)
87
[533:528]
IN1 of LUT3_9 or nRST (nSET) of DFF13
Delay1 Input (or Counter1 nRST Input)
88
[539:534]
IN2 of LUT3_9 or Data of DFF13
Delay1 Input (or Counter1 nRST Input)
89
[545:540]
IN0 of LUT3_10 or CLK Input of DFF14
Delay2 Input (or Counter2 nRST Input)
90
[551:546]
IN1 of LUT3_10 or nRST (nSET) of DFF14
Delay2 Input (or Counter2 nRST Input)
91
[557:552]
IN2 of LUT3_10 or Data of DFF14
Delay2 Input (or Counter2 nRST Input)
92
[563:558]
IN0 of LUT3_11 or CLK Input of DFF15
Delay3 Input (or Counter3 nRST Input)
93
[569:564]
IN1 of LUT3_11 or nRST (nSET) of DFF15
Delay3 Input (or Counter3 nRST Input)
94
[575:570]
IN2 of LUT3_11 or Data of DFF15
Delay3 Input (or Counter3 nRST Input)
95
Note 1 For each Address, the two most significant bits are unused.
Table 23: Matrix Output Table (continued)
Register Bit
Address
Matrix Output Signal Function
Matrix Output
Number



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