VSC8541XMV-05 datasheet(28/101 Pages) MICROCHIP

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Functional Descriptions

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

registers. The register set that controls the SMI consists of 32 16-bit registers, including all required

IEEE-specified registers. Additional pages of registers are accessible using device register 31.

Energy-efficient Ethernet control registers are available through the SMI using Clause 45 registers and

Clause 22 register access in registers 13 through 14.

The SMI is a synchronous serial interface with input data to the VSC8541-02 device on the MDIO pin that

is clocked on the rising edge of the MDC pin. The output data is sent on the MDIO pin on the rising edge

of the MDC signal. The interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending on the

total load on MDIO. An external 2 k

Ω pull-up resistor is required on the MDIO pin.

3.10.1

SMI Frames

Data is transferred over the SMI using 32-bit frames with an optional, arbitrary-length preamble. Before

the first frame can be sent, at least two clock pulses on MDC must be provided with the MDIO signal at

logic one to initialize the SMI state machine. The following illustrations show the SMI frame format for

read and write operations.

Figure 14 •

SMI Read Frame

Figure 15 •

SMI Write Frame

The following list defines the terms used in the SMI read and write timing diagrams.

•

Idle—During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up

resistor to pull the MDIO node up to a logical 1 state. Because the idle mode does not contain any

transitions on MDIO, the number of bits is undefined during idle.

•

Preamble—By default, preambles are not expected or required. The preamble is a string of ones. If

it exists, the preamble must be at least 1 bit; otherwise, it can be of an arbitrary length.

•

Start of Frame Delimiter (SFD—A pattern of 01 indicates the start of frame. If the pattern is not 01,

all following bits are ignored until the next preamble pattern is detected.

•

Read or Write Opcode—A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits

are not either 01 or 10, all following bits are ignored until the next preamble pattern is detected.

•

PHY Address—The particular VSC8541-02 device responds to a message frame only when the

received PHY address matches its physical address. The physical address is 5 bits long (4:0).

•

Turnaround—The two bits used to avoid signal contention when a read operation is performed on

the MDIO are called the turnaround (TA) bits. During read operations, the VSC8541-02 device drives

the second TA bit, a logical 0.

MDIO

Idle Preamble

(optional)

SFD

Read

MDC

Station manager drives MDIO

PHY drives MDIO

PHY Address

to PHY

from PHY

Idle

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

D0 Z

MDIO

Idle Preamble

(optional)

SFD

Write

MDC

Station manager drives MDIO (PHY tri-states MDIO during the entire sequence)

PHY Address

to PHY

Idle

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

D0 Z

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