VSC8541XMV-05 datasheet(65/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

4.4.11

Extended Interrupt Mask

The following table shows the register settings for the extended interrupt mask at address 28E2.

4.4.12

Extended Interrupt Status

The following table shows the register settings for the extended interrupt status at address 29E2.

7:5

Pad edge rate control

R/W

Sticky bit.

MAC interface edge rate control.

000: Slowest edge rate

001: +1 pad edge rate

010: +2 pad edge rate

011: +3 pad edge rate

100: +4 pad edge rate

101: +5 pad edge rate

110: +6 pad edge rate

111: +7 pad edge rate (fastest)

111

RMII CLKOUT enable

R/W

Sticky bit.

0: RMII CLKOUT disabled.

1: RMII CLKOUT enabled.

3:1

Reserved

Reserved.

MDINT CMOS drive

R/W

Sticky bit.

0: Disabled.

1: Enabled.

Table 68 •

Extended Interrupt Mask, Address 28E2 (0x1C)

Bit

Name

Access Description

Default

15:14

Reserved

Reserved.

Rx FIFO overflow/underflow interrupt mask

R/W

Sticky bit. 1: Enabled.

Tx FIFO overflow/underflow interrupt mask

R/W

Sticky bit. 1: Enabled.

11:5

Reserved

Reserved.

RR switchover complete interrupt mask

R/W

Sticky bit. 1: Enabled.0

EEE link fail interrupt mask

R/W

Sticky bit. 1: Enabled.

EEE Rx TQ timer interrupt mask

R/W

Sticky bit. 1: Enabled.

EEE wait quiet/Rx TS timer interrupt mask

R/W

Sticky bit. 1: Enabled.

EEE wake error interrupt mask

R/W

Sticky bit. 1: Enabled.

Table 69 •

Extended Interrupt Status, Address 29E2 (0x1D)

Bit

Name

Access Description

Default

15:14

Reserved

Reserved.

Rx FIFO overflow/underflow interrupt status

Self-clearing bit.

1: Interrupt pending.

Tx FIFO overflow/underflow interrupt status

Self-clearing bit.

1: Interrupt pending.

11:5

Reserved

Reserved.

Table 67 •

WoL and MAC Interface Control, Address 27E2 (0x1B) (continued)

Bit

Name

Access Description

Default

VSC8541XMV-05 Datasheet(PDF) 65 Page - Microchip Technology

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