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VSC8541XMV-05 Datasheet(PDF) 56 Page - Microchip Technology

Part # VSC8541XMV-05
Description  Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces
PDF  101 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

VSC8541XMV-05 Datasheet(HTML) 56 Page - Microchip Technology

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Registers
VMDS-10513 VSC8541-02 Datasheet Revision 4.1
47
4.3.4
PoE and Miscellaneous Functionality
The register at address 23E1 controls various aspects of inline-powering and the CRC error counter in
the VSC8541-02 device.
10
Slow MDC
R/W
Sticky bit.
1: Indicates that MDC runs at less than
1 MHz (use of this bit is optional and
indicated when MDC runs at less than
1MHz).
0
9:8
Reserved
RO
Reserved.
7:6
Media mode status
RO
00: No media selected.
01: Copper media selected.
10: Reserved.
11: Reserved.
00
5
Enable 10BASE-T no preamble mode
R/W
Sticky bit.
1: 10BASE-T will assert RX_DV indication
when data is presented to the receiver even
without a preamble preceding it.
0
4
Enable link speed autodownshift feature
R/W
Sticky bit.
1: Enable auto link speed downshift from
1000BASE-T.
0
3:2
Link speed auto downshift control
R/W
Sticky bit.
00: Downshift after 2 failed 1000BASE-T
auto-negotiation attempts.
01: Downshift after 3 failed 1000BASE-T
auto-negotiation attempts.
10: Downshift after 4 failed 1000BASE-T
auto-negotiation attempts.
11: Downshift after 5 failed 1000BASE-T
auto-negotiation attempts.
01
1
Link speed auto downshift status
RO
0: No downshift.
1: Downshift is required or has occurred.
0
0
Reserved
RO
Reserved.
Table 54 •
Extended PHY Control 4, Address 23E1 (0x17)
Bit
Name
Access
Description
Default
15:11
PHY address
RO
Internal PHY address: 0–31.
10
Inline powered device
detection
R/W
Sticky bit.
1: Enabled.
0
9:8
Inline powered device
detection status
RO
Only valid when bit 10 is set.
00: Searching for devices.
01: Device found; requires inline-power.
10: Device found; does not require inline-power.
11: Reserved.
00
7:0
Cu Media CRC error
counter
RO
Self-clearing 8-bit error count register.
Table 53 •
Extended PHY Control 3, Address 20E1 (0x14) (continued)
Bit
Name
Access Description
Default



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