VSC8541XMV-05 datasheet(70/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

4.6.2

PCS Status 1

The bits in the PCS Status 1 register provide a status of the EEE operation from the PCS for the link that

is currently active.

4.6.3

EEE Capability

This register is used to indicate the capability of the PCS to support EEE functions for each PHY type.

The following table shows the bit assignments for the EEE capability register.

4.6.4

EEE Wake Error Counter

This register is used by PHY types that support EEE to count wake time faults where the PHY fails to

complete its normal wake sequence within the time required for the specific PHY type. The definition of

the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as

defined by the PHY. This 16-bit counter is reset to all zeros when the EEE wake error counter is read or

when the PHY undergoes hardware or software reset.

Table 79 •

PCS Status 1, Address 3.1

Bit

Name

Access Description

15:12 Reserved

Reserved.

Tx LPI received

RO/LH

1: Tx PCS has received LPI.

0: LPI not received.

Rx LPI received

RO/LH

1: Rx PCS has received LPI.

0: LPI not received.

Tx LPI indication

1: Tx PCS is currently receiving LPI.

0: PCS is not currently receiving LPI.

Rx LPI indication

1: Rx PCS is currently receiving LPI.

0: PCS is not currently receiving LPI.

7:3

Reserved

Reserved.

PCS receive link status RO/LL

1: PCS receive link up.

0: PCS receive link down.

1:0

Reserved

Reserved.

Table 80 •

EEE Capability, Address 3.20

Bit

Name

Access Description

15:3 Reserved

Reserved.

1000BASE-T EEE

1: EEE is supported for 1000BASE-T.

0: EEE is not supported for 1000BASE-T.

100BASE-TX EEE

1: EEE is supported for 100BASE-TX.

0: EEE is not supported for 100BASE-TX.

Reserved

Reserved.

Table 81 •

EEE Wake Error Counter, Address 3.22

Bit

Name

Access Description

15:0 Wake error counter RO

Count of wake time faults for a PHY

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