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VSC8541XMV-05 Datasheet(PDF) 90 Page - Microchip Technology |
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VSC8541XMV-05 Datasheet(HTML) 90 Page - Microchip Technology |
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90 / 101 page  Pin Descriptions VMDS-10513 VSC8541-02 Datasheet Revision 4.1 81 Functional Group Name Number Type I/O Domain Description Cu PHY Media P0_D0N 12 ADIFF VDD25A Tx/Rx channel A negative signal Cu PHY Media P0_D0P 13 ADIFF VDD25A Tx/Rx channel A positive signal Cu PHY Media P0_D1N 9 ADIFF VDD25A Tx/Rx channel B negative signal Cu PHY Media P0_D1P 10 ADIFF VDD25A Tx/Rx channel B positive signal Cu PHY Media P0_D2N 6 ADIFF VDD25A Tx/Rx channel C negative signal Cu PHY Media P0_D2P 7 ADIFF VDD25A Tx/Rx channel C positive signal Cu PHY Media P0_D3N 3 ADIFF VDD25A Tx/Rx channel D negative signal Cu PHY Media P0_D3P 4 ADIFF VDD25A Tx/Rx channel D positive signal Miscellaneous REF_FILT 67 A VDD25A Reference filter connects to an external 0.01 uF (20%) capacitor to analog ground Miscellaneous REF_REXT 1 A VDD25A Reference connects to an external 2k Ω (1%) resistor to analog ground Miscellaneous RESERVED_0 66 VDD25A Reserved signal, leave unconnected Miscellaneous RESERVED_1 65 VDD25A Reserved signal, leave unconnected Miscellaneous THERMDA 15 A VDD25A Thermal Diode Anode Miscellaneous THERMDC_VSS 16 A VDD25A Thermal Diode Cathode connected to device ground. Temperature sensor must be chosen accordingly. PHY Configuration CLK_SQUELCH_IN 57 I, PD VDDIO Input control to squelch recovered clock PHY Configuration CLKOUT 54 I/O, PD VDDIO Clock output, can be enabled or disabled. Output a clock based on the local reference clock with programmable frequency. This pin is not active when NRESET is asserted and is disabled by default. When disabled, the pin is held low. The logic state on this pin is latched on the rising edge of NRESET to configure CLKOUT output. See "Hardware Mode Strapping and PHY Addressing" for details. PHY Configuration COMA_MODE 56 I/O, PU VDDIO When this pin is asserted high, PHY is held in a powered down state. When de- asserted low, PHY is powered up and resumes normal operation. This signal is also used to synchronize the operation of multiple chips on the same PCB to provide visual synchronization for LEDs driven by separate chips. PHY Configuration FASTLINK_FAIL 52 O VDDIO Fast link failure indication signal PHY Configuration LED0 60 O VDDIO LED direct drive outputs. All LED pins are active low. LED_DATA output in serial LED mode. |
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