VSC8541XMV-05 datasheet(98/101 Pages) MICROCHIP

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Design Considerations

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

Design Considerations

This section provides information about design considerations for the VSC8541-02 device.

8.1

Link status LED remains on while COMA_MODE pin is

asserted high

When the COMA_MODE is asserted high, the link status LED may not deactivate unless the media cable

is disconnected from the device.

While using COMA_MODE, link status should be verified using status registers rather than LED

indicators.

8.2

Forced 1000BASE-T mode blocks some SMI register

writes

When hardware strapping pins are used to force 1000BASE-T mode (as described in Forced

1000BASE-T Mode, page 11), register writes to some serial management interface (SMI) registers are

not allowed.

As a workaround for this issue when using hardware strapping pins to force 1000BASE-T mode, execute

the following register writes before performing any other SMI register writes to the device.

Write 0x0000 to register address 31.

Read register address 9.

Modify read back value and set bits 15:13 to 0.

Write updated value to register address 9.

After performing steps 1–4, all SMI register writes behave normally.

8.3

Forced 1000BASE-T mode incorrectly reports interrupt

status and PCS status counters

When operating in Forced 1000BASE-T mode, the device does not report interrupt status correctly within

the interrupt status register (see Interrupt Status, page 42). In addition, the device does not correctly

report 1000BASE-T Status Extension 2 (see 1000BASE-T Status Extension 2, page 37) or error counts

(see Error Counter 1, page 38, Error Counter 2, page 39, and Error Counter 3, page 39).

Contact Microsemi for more information.

8.4

10BASE-T signal amplitude

10BASE-T signal amplitude can be lower than the minimum specified in IEEE 802.3 paragraph

14.3.1.2.1 (2.2 V) at low supply voltages. Additionally, associated templates may be marginal or have

failures.

This issue is not estimated to present any system-level impact. Performance is not impaired with cables

up to 130 m with various link partners.

8.5

Receive error counter only clears when NRESET applied

in RMII mode

When operating in RMII MAC interface mode, the receive error counter of register 19 (Table 38, page 38)

does not clear upon read-back or software reset of the device. The only way to clear this register while in

RMII mode is to assert the NRESET pin of the device.

The receive error counter at register address 19 operates normally in MAC interface modes other than

RMII.

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