AMD-K6-2ESLASH233AMZ datasheet(198/332 Pages) AMD

198 / 332 page

180

Power-On Configuration and Initialization

Chapter 7

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

7.2

RESET Requirements

During the initial power-on reset of the processor, RESET must

remain asserted for a minimum of 1.0 ms after CLK and VCC

reach specification. (See “CLK Switching Characteristics” on

page 267 for clock specifications. See “Electrical Data” on page

253 for VCC specifications.)

D u r i n g a w a r m re set while CLK and V CC are wit h in

specification, RESET must remain asserted for a minimum of

15 clocks prior to its negation.

7.3

State of Processor After RESET

Output Signals

Table 29 show s the state of all proc essor outputs and

bidirectional signals immediately after RESET is sampled

asserted.

Registers

Table 30 on page 181 shows the state of all architecture

registers and Model-Specific Registers (MSRs) after the

processor has completed its initialization due to the recognition

of the assertion of RESET.

Table 29. Output Signal State After RESET

Signal

State

Signal

State

A[31:3], AP

Floating

LOCK#

High

ADS#, ADSC#

High

M/IO#

Low

APCHK#

High

PCD

Low

BE[7:0]#

Floating

PCHK#

High

BREQ

Low

PWT

Low

CACHE#

High

SCYC

Low

D/C#

Low

SMIACT#

High

D[63:0], DP[7:0]

Floating

TDO

Floating

FERR#

High

VCC2DET

Low

HIT#

High

VCC2H/L#

Low

HITM#

High

W/R#

Low

HLDA

Low

––

AMD-K6-2E/233AMZ Datasheet(PDF) 198 Page - Advanced Micro Devices

AMD-K6-2E/233AMZ Datasheet(HTML) 198 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL