AMD-K6-2ESLASH233AMZ datasheet(218/332 Pages) AMD

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Cache Organization

Chapter 8

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

cache during read misses to its instruction cache. Table 35

summarizes the actions taken during this internal snooping.

If an internal snoop hits its target, the processor does the

following:

Data Cache Snoop During an Instruction-Cache Read

Miss—If modified, the line in the data cache is written back

on the system bus to external memory. Regardless of its

state, the data-cache line is invalidated and the instruction

cache performs a burst read cycle from external memory.

Instruction Cache Snoop During a Data-Cache Miss —The

line in the instruction cache is marked invalid, and the

data-cache read or write is performed from memory.

FLUSH#

In response to sampling FLUSH# asserted, the processor writes

back any data cache lines that are in the Modified state and

then marks all lines in the instruction and data caches as

invalid.

Page Flush/Invalidate

The AMD-K6-2E processor contains the page flush/invalidate

and optional flushing of a specific 4-Kbyte page from the linear

address space. When the PFIR is written to (using the WRMSR

instruction), the invalidation and the flushing (optional) begin.

The total amount of cache in the AMD-K6-2E processor is 64

Kbytes. Using this register can result in a much lower cycle

count for flushing particular pages versus flushing the entire

cache.

Figure 78. Page Flush/Invalidate Register (PFIR)—MSR C000_0088h

LINPAGE

Symbol

Description

Bit

LINPAGE

20-bit Linear Page Address

31-12

Page Fault Occurred

F/I

Flush/Invalidate Command

98 7

Reserved

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