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AMD-K6-2E/233AMZ Datasheet(PDF) 217 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ Datasheet(HTML) 217 Page - Advanced Micro Devices |
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217 / 332 page ![]() Chapter 8 Cache Organization 199 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information 8.10 Cache Coherency Different methods exist to maintain coherency between the system memory and cache memories. Inquire cycles, internal snoops, FLUSH#, WBINVD, INVD, and line replacements all prevent inconsistencies between memories. Inquire Cycles Inquire cycles are bus cycles initiated by system logic. These inquiries ensure coherency between the caches and main memory. In systems with multiple caching masters, system logic maintains cache coherency by driving inquire cycles to the processor. System logic initiates inquire cycles by asserting AHOLD, BOFF#, or HOLD to obtain control of the address bus and then driving EADS#, INV (optional), and an inquire address (A[31:5]). This type of bus cycle causes the processor to compare the tags for both its instruction and data caches with the inquire address. s If there is a hit to a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts HIT#. s If the compare hits a modified line in the data cache, the processor asserts HIT# and HITM#. If HITM# is asserted, the processor writes the modified line back to memory. s If INV was sampled asserted with EADS#, a hit invalidates the line. s If INV was sampled negated with EADS#, a hit leaves the line in the Shared state or transitions it from the Exclusive or Modified to Shared state. Table 35 on page 202 shows the effects of inquire cycles— performed with INV equal to 0 (non-validating) and INV equal to 1 (invalidating) snoops and invalidations. Internal Snooping Internal snooping is initiated by the processor (rather than system logic) during certain cache accesses. It is used to maintain coherency between the L1 instruction and data caches. The processor automatically snoops its instruction cache during read or write misses to its data cache, and it snoops its data |
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