AMD-K6-2ESLASH233AMZ datasheet(213/332 Pages) AMD

213 / 332 page

Chapter 8

Cache Organization

195

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

write allocates can still occur between 15 Mbytes and 16

Mbytes due to the “Write to a Cacheable Page” and “Write to a

Sector” mechanisms). The WAE15M bit is ignored if the value

in the WAELIM field is less than 16 Mbytes.

By definition, a write allocate is never performed in the

memory area between 640 Kbytes and 1 Mbyte unless the

processor determines a pending write cycle is cacheable by

means of one of the other write allocate mechanisms —“Write

to a Cacheable Page” and “Write to a Sector”. It is not

considered safe to perform write allocations between 640

Kbytes and 1 Mbyte (000A_0000h to 000F_FFFFh) because it is

considered a noncacheable region of memory.

If a memory region is defined as w rite- combin ab le or

uncacheable by a MTRR, write allocates are not performed in

that region.

Write Allocate Logic

Mechanisms and

Conditions

Figure 77 shows the logic flow for all the mechanisms involved

with write allocate for memory bus cycles. The left side of the

diagram (the text) describes the conditions that need to be true

for the value of that line to be a 1. Items 1–4 of the diagram are

related to general cache operation and items 5–10 are related to

the write allocate mechanisms.

Fo r mor e inf o r m a t i o n a b out wri t e all o c a te, see the

Implementation of Write Allocate in the K86™ Processors

Application Note, order #21326.

Figure 77. Write Allocate Logic Mechanisms and Conditions

1) CD Bit of CR0

Perform

Write Allocate

3) CI Bit of TR12

2) PCD Signal

5) Write to Cacheable Page (CCR)

6) Write to a Sector

8) Between 640 Kbytes and 1 Mbyte

7) Less Than Limit (WAELIM)

9) Between 15–16 Mbytes

10) Write Allocate Enable 15–16 Mbyte (WAE15M)

4) UC or WC

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