AMD-K6-2ESLASH233AMZ datasheet(211/332 Pages) AMD

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Chapter 8

Cache Organization

193

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

negated, the processor does not perform an allocation. In this

case, the pending write cycle is executed as a single write cycle

on the system bus.

During write allocates, a 32-byte burst read cycle is executed in

place of a non-burst write cycle. While the burst read cycle

generally takes longer to execute than the write cycle,

performance gains are realized on subsequent write cycle hits

to the write-allocated cache line. Due to the nature of software,

memory accesses tend to occur in proximity of each other

(principle of locality). The likelihood of additional write hits to

the write-allocated cache line is high.

The following is a description of three mechanisms by which the

AMD-K6-2E processor performs write allocations. A write

a l l o ca te i s perfor med w h e n any one or more o f thes e

mechanisms indicates that a pending write is to a cacheable

area of memory.

Write to a Cacheable

Page

Every time the processor performs a cache line fill, the address

of the page in which the cache line resides is saved in the

Cacheability Control Register (CCR). The page address of

subsequent write cycles is compared with the page address

stored in the CCR. If the two addresses are equal, then the

processor performs a write allocate because the page has

already been determined to be cacheable.

When the processor performs a cache line fill from a different

page than the address saved in the CCR, the CCR is updated

with the new page address.

Write to a Sector

If the address of a pending write cycle matches the tag address

of a valid cache sector, but the addressed cache line within the

sector is marked invalid (a sector hit but a cache line miss),

then the processor performs a write allocate. The pending write

cycle is determined to be cacheable because the sector hit

indicates the presence of at least one valid cache line in the

sector. The two cache lines within a sector are guaranteed by

design to be within the same page.

Write Allocate Limit

The AMD-K6-2E processor uses two mechanisms that are

programmable within the Write Handling Control register

(WHCR) to enable write allocations for write cycles that

address a definable or special 1-Mbyte memory area.

AMD-K6-2E/233AMZ Datasheet(PDF) 211 Page - Advanced Micro Devices

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