AMD-K6-2ESLASH233AMZ datasheet(210/332 Pages) AMD

210 / 332 page

192

Cache Organization

Chapter 8

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

8.6

Cache-Line Replacements

As programs execute and task switches occur, some cache lines

eventually require replacement.

Instruction cache lines are replaced using a Least Recently

Used (LRU) algorithm. If line replacement is required, lines are

replaced when read cache misses occur.

The data cache uses a slightly different approach to line

replacement. If a miss occurs, and a replacement is required,

lines are replaced by using a Least Recently Allocated (LRA)

algorithm.

Two forms of cache misses and associated cache fills can take

place—a tag-miss cache fill and a tag-hit cache fill.

In the case of a tag-miss cache fill, the miss is due to a tag

mismatch, in which case the required cache line is filled

from external memory, and the cache line within the sector

that was not required is marked as invalid.

In the case of a tag-hit cache fill, the address matches the

tag, but the requested cache line is marked as invalid. The

required cache line is filled from external memory, and the

cache line within the sector that is not required remains in

the same cache state.

8.7

Write Allocate

Write allocate, if enabled, occurs when the processor has a

pending memory write cycle to a cacheable line and the line

does not currently reside in the data cache. In this case, the

processor performs a 32-byte burst read cycle to fetch the

data-cache line addressed by the pending write cycle. The data

associated with the pending write cycle is merged with the

recently-allocated data-cache line and stored in the processor’s

data cache. The final MESI state of the cache line depends on

the state of the WB/WT# and PWT signals during the burst read

cycle and the subsequent data cache write hit (See Table 34 on

page 198 to determine the cache-line states and the access

types following a cache read miss and cache write hit).

If a data-cache line fetch from memory is attempted because

the write allocate misses the data cache, and KEN# is sampled

AMD-K6-2E/233AMZ Datasheet(PDF) 210 Page - Advanced Micro Devices

AMD-K6-2E/233AMZ Datasheet(HTML) 210 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL