AMD-K6-2ESLASH233AMZ datasheet(206/332 Pages) AMD

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188

Cache Organization

Chapter 8

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

lines cause external memory updates. If PWT is driven Low

and WB/WT# is sampled High, a write hit to a shared line

changes the cache-line state to Exclusive.

When the CD and NW bits are both 1, the cache is fully

disabled. Even though the cache is disabled, the contents

are not necessarily invalid. The processor reads from the

cache and, if a read miss occurs, no line fills take place. If a

write hit occurs, the cache is updated but an external

memory update does not occur. If a cache line is in the

Exclusive state during a write hit, the cache-line state is

changed to Modified. Cache lines in the Shared state remain

in the Shared state after a write hit. Write misses access

external memory directly.

The operating system can control the cacheability of a page.

The paging mechanism is controlled by CR3, the Page Directory

Entry (PDE), and the Page Table Entry (PTE). Within CR3,

PDE, and PTE are Page Cache Disable (PCD) and Page

Writethrough (PWT) bits. The values of the PCD and PWT bits

used in Table 31 and Table 32 are taken from either the PTE or

PDE. For more information see the descriptions of PCD and

PWT on page 115 and page 117, respectively.

Tables 31 through 33 describe the logic that determines the

cacheability of a cycle and how that cacheability is affected by

the PCD bits, the PWT bits, the PG and CD bits of CR0,

writeback cycles, the Cache Inhibit (CI) bit of Test Register 12

(TR12), and unlocked memory reads.

Table 31 describes how the PWT signal is driven based on the

values of the PWT bits and the PG bit of CR0.

Table 31. PWT Signal Generation

PWT Bit1

Notes:

PWT is taken from PTE or PDE.

PG Bit of CR0

PWT Signal

High

Low

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