AMD-K6-2ESLASH233AMZ datasheet(203/332 Pages) AMD

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Chapter 8

Cache Organization

185

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Cache Organization

The following sections describe the basic architecture and

resources of the AMD-K6-2E processor internal caches.

The performance of the AMD-K6-2E processor is enhanced by a

writeback level-one (L1) cache. The cache is organized as a

separate 32-Kbyte instruction cache and a 32-Kbyte data cache,

each with two-way set associativity (See Figure 74). The cache

line size is 32 bytes, and lines are prefetched from external

memory using an efficient, pipelined burst transaction.

As the instruction cache is filled, each instruction byte is

analyzed for instruction boundaries using predecode logic.

Predecoding annotates each instruction byte with information

that later enables the decoders to efficiently decode multiple

instructions simultaneously. Translation lookaside buffers

(TLB) are also used to translate linear addresses to physical

addresses. The instruction cache is associated with a 64-entry

TLB, while the data cache is associated with a 128-entry TLB.

Figure 74. Cache Organization

Processor

Core

System Bus

Interface Unit

128-Entry TLB

64-Entry TLB

State

Bit

Tag

RAM

Way 0

Way 1

State

Bit

Tag

RAM

32-Kbyte Instruction Cache

32-Kbyte Data Cache

Predecode Instruction Cache

MESI

Bits

Tag

RAM

Way 0

Way 1

MESI

Bits

Tag

RAM

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