AMD-K6-2ESLASH233AMZ datasheet(205/332 Pages) AMD

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Chapter 8

Cache Organization

187

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

8.2

Predecode Bits

Decoding x86 instructions is particularly difficult because the

instructions vary in length, ranging from 1 to 15 bytes long.

Predecode logic supplies the predecode bits associated with

each instruction byte.

Predecode bits indicate the number of bytes to the start of the

next x86 instruction. The predecode bits are passed with the

instruction bytes to the decoders, where they assist with

parallel x86 instruction decoding. The predecode bits use

memory separate from the 32-Kbyte instruction cache. The

predecode bits are stored in an extended instruction cache

alongside each x86 instruction byte as shown in Figure 75 on

page 186.

8.3

Cache Operation

The operating modes for the caches are configured by software

using the Not Writethrough (NW) and Cache Disable (CD) bits

of control register 0 (CR0 bits 29 and 30 respectively). These

bits are used in all operating modes.

When the CD and NW bits are both 0, the cache is fully

enabled. This is the standard operating mode for the cache.

If a read miss occurs when the processor reads from the

cache, a line fill (32-byte burst read) on the system bus

occurs in order to fetch the cache line. Write hits to the

cache are updated, while write misses and writes to shared

lines cause external memory updates. Refer to Table 34,

“Data Cache States for Read and Write Accesses,” on

page 198 for a summary of cache read and write cycles and

the effect of these operations on the cache MESI state.

Note: A write allocate operation can modify the behavior of write

misses to the cache. See “Write Allocate” on page 192.

When the CD bit is 0 and the NW bit is 1, an invalid mode of

operation exists that causes a general protection fault to

occur.

When the CD bit is 1 (disabled) and the NW bit is 0, the

cache fill mechanism is disabled but the contents of the

cache are still valid. The processor reads from the cache, and

if a read miss occurs, no line fills take place. Write hits to the

cache are updated, while write misses and writes to shared

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