AD4080BBCZ datasheet(30/95 Pages) AD

30 / 95 page

Data Sheet

AD4080

APPLICATIONS INFORMATION

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are not available for alignment, the ADC Result Latency and LVDS

Interface Alignment section describes how the INTF_CHK_EN bit

(Address 0x15, Bit 4) can be enabled to help align the host control-

ler to data and to mitigate against any system propagation delays.

Figure 46. Single Lane, LVDS Data Interface Clocking Example

Figure 47. Dual Lane, LVDS Data Interface Clocking Example

In cases where the SPI data interface (see the SPI Data Interface

section) is used to access conversion results from the result FIFO

(see the Result FIFO section) again, it is important that the CNV

source jitter is carefully considered to achieve the required perform-

ance. In the case shown in the SPI data interface clocking example

(see Figure 48) , an oscillator directly provides the conversion

clock, and the data is asynchronously clocked from the FIFO by

a microcontroller unit (MCU). Optionally, as shown in Figure 48,

the general-purpose input and output pins can be configured to

control the result FIFO operation (see the GPIO Pins section and

the Result FIFO section).

Figure 48. SPI Data Interface Clocking Example

POWER SOLUTION

With such low noise and up to a 40 MHz sampling rate, it is

important that careful consideration is taken for the power solution

of applications to ensure that the low noise supplies provided to the

AD4080 do not become a source of performance or accuracy deg-

radation. To aid ease of use and to help reduce external required

components, two internal LDO regulators are integrated within the

AD4080. Further details on these regulators can be found in the

Internally Regulated Supply Configuration section. Also, note that

the internal supply decoupling capacitors are included for all supply

rails, whether generated internally or externally, reducing external

component count, simplifying use, and offering huge benefits to

PCB layout, routing, and design density.

For externally generated supply rails, excellent choice LDO regula-

tors are the LT3045 or ADP150, which both offer ultra-low noise

and excellent power supply rejection. For high efficiency, step-down

switching regulators, the LT8604C is a good choice; however, great

care must be taken in the design of the switching regulator circuity

because switching frequencies are likely to be within the application

signal bandwidth, and although the AD4080 has high AC power

supply rejection on its supplies, appropriate consideration must be

given to the supply rails.

AD4080BBCZ Datasheet(PDF) 30 Page - Analog Devices

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