AD4080BBCZ datasheet(35/95 Pages) AD

35 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

analog.com

Rev. 0 | 35 of 95

Address Ascension Selection

The address ascension selection (ADDR_ASCENSION) bit, as de-

scribed in previous sections, determines how the internal interface

address pointer is updated for each byte of data transmitted to the

AD4080 in streaming mode (SINGLE_INST = 0). If using single

instruction mode (SINGLE_INST = 1), each register is directly

addressed through its own instruction phase as illustrated in Figure

54, and thus, the address pointer is not updated. Regardless of

the setting for SINGLE_INST, the ADDR_ASCENSION bit directly

impacts the formatting of the SPI frame in terms of selection of

the instruction phase starting address and byte order of the data

phase payload. This impact is described in greater detail in the

Strict Access Selection and Multibyte Registers section as much

of the data formatting is dependent on this interface configuration

selection. The ADDR_ASCENSION selection bit is located in the

Interface Configuration A register (see the Interface Configuration A

As summarized in Table 15, the ADDR_ASCENSION bit is cleared

by default, resulting in the address pointer decrementing by one

for each data byte transmitted. In this decrement configuration

(ADDR_ASCENSION = 0), the address pointer decrements from

the starting address indicated in the instruction phase by one for

each data phase byte received until the counter reaches Address

0x0000. If additional bytes are received, the pointer automatically

rolls over to the maximum address value, 0x7FFF; the rollover

behavior is fixed, and therefore, independent of the SHORT_IN-

STRUCTION value or the physical address space occupied by the

user configurable registers. It is important to understand this behav-

ior to avoid generating interface errors associated with attempting

to access one or more invalid register addresses. Limit register

access to the register address space associated with the device

configuration as described in the Configuration Registers section.

Alternatively, the ADDR_ASCENSION bit can be set (ADDR_AS-

CENSION = 1), resulting in the address pointer incrementing by

one, starting at the address identified in the instruction word, for

each data phase byte received at the AD4080 in a given SPI

frame. In a manner similar to the descending case, the address

counter continues to increment for each data byte received until

the maximum address value, 0x7FFFF, is reached, after which the

pointer rolls over to 0x0000.

Strict Access Selection and Multibyte

Registers

Several locations in the AD4080 configuration memory have been

assigned as multibyte registers to support the storage require-

ments. For example, the offset correct register (see the Offset

Correction Register section, Address 0x25) and gain correction

are multibyte registers because the resolution of the correction

coefficients they contain exceeds a single byte. For a complete

listing of multibyte registers, refer to the Configuration Registers

section. The length of each register, in bytes, is captured in Table

31 in addition to other characteristic information.

The function of the STRICT_REGISTER_ACCESS bit is to indicate

to the interface controller that all bytes of a multibyte register must

be accessed in the current frame for valid communication to have

occurred. In the event a multibyte register is only partially accessed,

an interface fault is generated in the Interface Status A register

(see the Interface Status A Register section, Address 0x11), and

the partial content update is discarded. The intent of this restriction

is to ensure that corresponding configuration quantities are updated

in a manner that produces the desired device operation. The

access restriction function is enabled by default (STRICT_REGIS-

TER_ACCESS = 1) and can be disabled by clearing the access bit

(STRICT_REGISTER_ACCESS = 0) in the Interface Configuration

C register (see the Interface Configuration C Register section,

Address 0x10). With register access restriction disabled, each byte

of the configuration memory can be independently addressed;

however, it is then incumbent on the software to correctly configure

any multibyte registers in the device memory to achieve the desired

behavior.

The decision to enable or disable the register access restriction

has implications with regards to the correct construction of the

SPI frames containing one or more multibyte register accesses.

When STRICT_REGISTER_ACCESS is disabled, each byte of a

multibyte register is treated as a singular element. Furthermore,

the interface does not indicate a fault if all bytes of the register

are not programmed, or if the bytes are programmed in a random

order, and therefore, it is incumbent on the host to ensure that the

content of those registers are updated in a manner that produces

the desired function in the device.

When STRICT_REGISTER_ACCESS is enabled, specific access

rules are enforced to ensure consistency between the data and the

expected behavior of the device. To understand how these rules

apply to multibyte registers in the configuration memory, it is impor-

tant to understand how the memory is organized. By convention,

multibyte registers are arranged in the configuration memory such

that the most significant byte of the register is stored in the most

significant address of the assigned register space as illustrated in

Figure 55. As a result, the byte order of the register content trans-

mitted in the data phase is dependent on the ADDR_ASCENSION

selection.

AD4080BBCZ Datasheet(PDF) 35 Page - Analog Devices

AD4080BBCZ Datasheet(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datasheet Download

Link URL