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AD4080BBCZ Datasheet(PDF) 67 Page - Analog Devices |
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AD4080BBCZ Datasheet(HTML) 67 Page - Analog Devices |
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67 / 95 page  Data Sheet AD4080 DIGITAL FEATURES analog.com Rev. 0 | 67 of 95 Filter Reset Conditions Direct LVDS When accessing the filtered data directly via the LVDS interface, the AD4080 resets the filter by the following two methods: ► By configuring the filter, by issuing a write to the filter configu- ration register, Bits[7:0] (see the Filter Configuration Register section, Address 0x29). ► By asserting a GPIO that’ is configured for FILTER_SYNC opera- tion. With FIFO When the FIFO is enabled, the user must use a GPIO configured as FILTER_SYNC to reset the filter for each FIFO acquisition. Filter Synchronization Set GPIO_x_SEL to FILTER_SYNC to configure this input providing synchronization to the controller of the user, which can be used to synchronize the filters across multiple AD4080 devices. The FILTER_SYNC signal is an active low input, and this signal must be held low for a minimum of one conversion cycle to reset and synchronize the digital filter. Refer to Figure 96 for the timing requirements for a filter reset. Figure 96. Filter Reset Timing |
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