AD4080BBCZ datasheet(20/95 Pages) AD

20 / 95 page

Data Sheet

AD4080

THEORY OF OPERATION

analog.com

Rev. 0 | 20 of 95

ensure that there is enough time to settle to the required voltage

accuracy (or ADC resolution). For this reason, a fast ADC requires

a wide bandwidth driver. For high resolution ADC converters, low

signal chain noise is required to obtain high resolution. A wider

bandwidth can result in more noise coming through the signal chain

to the ADC, which can present a significant signal chain design

challenge for a conventional SAR ADC. However, the AD4080 in-

cludes some unique Easy Drive features that simplify these aspects

of signal chain design.

One such AD4080 feature is continuous signal acquisition. Due

to its unique design, that the tAQC is equal to the tCYC of the

ADC, resulting in the AD4080 being in signal acquisition mode

for the full duration of each ADC conversion. The input voltage

has 100% of the tCYC conversion time to settle the input voltage

before the next conversion, whereas a conventional ADC may need

to settle in 60% of this time. More settling time results in less

bandwidth required by the driver, which generally, bears a lower

power requirement. In addition, because the external filters (RFILTIN

and CFILTIN) must be designed with enough bandwidth for the driver

to settle the input voltage, the additional settling time results in a

lower cut-off. Because of this lower cut-off, more of the signal chain

noise can be filtered at the inputs with these external filters.

Another Easy Drive feature is its highly linearized analog input

current. With this feature, the AD4080 presents a less challenging

load to a driver amplifier and reduces any potential distortion from

a driver that can occur when presented with a nonlinear input

current. Figure 34 shows the typical input currents into both the

differential signal pair (IN+ and IN−) and auxiliary inputs (AUXIN+

and AUXIN−).

Figure 34. Typical Input Current vs. Differential Input Voltage

To design the external input filter, it is usual to calculate how

many time constants (K) are needed for the required resolution.

To calculate the time constant from the natural log of the required

setting resolution, for example, if settling to within 1 LSB of 20 bits

(n = 20) of resolution is desired, use the following equation:

K = ln(2n ∕ 1 bit) = 13.86 time constants

(1)

When considering a conventional ADC, as described in the Con-

verter Operation section, where the acquisition time is only 60% of

the ADC conversion cycle, there is less time available for settling.

For such an ADC sampling at 40 MSPS, the driver must settle

within 25 ns × 0.6 or 15 ns, and settling of the input voltage within 1

LSB also requires a time constant tau (τ) of 15 ns ÷ K = 1.082 ns or

a bandwidth of 1/(2 × π × τ) = 147 MHz.

However, with the Easy Drive features of the AD4080, the result

is an acquisition time of 100% of the conversion cycle, which

indicates only 13.86 time constants to settle within 1 LSB of 20 bits

resolution. However, additionally, the low analog input current of

the AD4080 and the internal methods that reduce any kick back to

the driver (as charge transfers from the analog input to the internal

sampling capacitors at the sampling instance) reduce the required

number of time constants by 9.5%. Therefore, for the 20-bit settling

example, the required number of time constants (K) reduces from

13.86 to 12.55 without impact on settling or distortion.

These Easy Drive features significantly reduce the required driver

bandwidth required to settle. For example, at 40 MSPS, settling of

the input voltage within 1 LSB requires a time constant tau (τ) of

25 ns ÷ K = 1.992 ns, or a bandwidth of 1/(2 × π × τ) = 80 MHz.

This significant reduction in the required bandwidth allows use of

lower power, lower bandwidth drivers and the design of a lower

bandwidth input filter to remove more driver or signal chain noise.

Table 8 suggests some filter values for use with the AD4080 in

some example use case conditions.

Another Easy Drive feature, as can be seen in the Figure 33, is the

auxiliary signal input path. This path feeds the analog input signal

to an internal linearization block, and this block feeds a correction

signal to the sampled voltage. Recommended values are given

in Table 8. The filter on the auxiliary inputs is set for the same

bandwidth as the analog input, and RFILTAUX must be set at 4 ×

RFILTIN. The recommended filter configuration is to use a differential

CFILTIN capacitor; therefore, calculate the components as τ = RFILTIN

× 2 × CFILTIN.

Note that the minimum RFILTIN must be 15 Ω, and that RFILTAUX can

be set from a minimum of 5 Ω up to 4 × RFILTIN .

Table 8. Recommended Input Filter Configurations

fS (MSPS)

Target Accuracy (Bit)

Required Bandwidth (MHz)

RFILTIN (Ω)

CFILTIN (pF)

RFILTAUX (Ω)

CFILTAUX (pF)

100

AD4080BBCZ Datasheet(PDF) 20 Page - Analog Devices

AD4080BBCZ Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datasheet Download

Link URL