AD4080BBCZ datasheet(82/95 Pages) AD

82 / 95 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Interface Status A Register

Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A

Status bits are set to 1 to indicate an active condition. These bits can be cleared by writing a 1 to the corresponding bit location.

Figure 122. Interface Status A Register

Table 46. Bit Descriptions for INTERFACE_STATUS_A

Bits

Bit Name

Description

Reset

Access

NOT_READY_ERR

Device Not Ready for Transaction. This bit is set if the user attempts to execute an SPI

transaction before the completion of digital initialization.

0x0

R/W1C

[6:5]

RESERVED

Reserved. Write 0b00 to these bits.

0x0

CLOCK_COUNT_ERR

Clock Count Error. This bit is set when an incorrect number of clocks is detected in a

transaction.

0x0

R/W1C

CRC_ERR

CRC Error. This bit is set when the SPI controller does not send a CRC or when the CRC

value calculated by the device does not match the value sent by the SPI controller.

0x0

R/W1C

WR_TO_RD_ONLY_REG_ERR

Write to Read Only Register Error. This bit is set when the user attempts a write to a register

that is read only.

0x0

R/W1C

REGISTER_PARTIAL_ACCESS_ERR

are read from or written to in a multibyte register access. This bit is only valid when strict

0x0

R/W1C

ADDRESS_INVALID_ERR

Invalid Address Error. This bit is set when the user tries to read from or write to a register

address outside of the allowed memory map space.

0x0

R/W1C

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