AD4080BBCZ datasheet(84/95 Pages) AD

84 / 95 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

analog.com

Rev. 0 | 84 of 95

ADC Data Interface Configuration A Register

Address: 0x15, Reset: 0x40, Name: ADC_DATA_INTF_CONFIG_A

Figure 124. ADC Data Interface Configuration A Register

Table 48. Bit Descriptions for ADC_DATA_INTF_CONFIG_A

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved. Write 0b0 to this bit.

0x0

RESERVED

Reserved. Always set this bit to 1.

0x1

R/W

RESERVED

Reserved. Write 0b0 to this bit.

0x0

INTF_CHK_EN

Output Fixed Test Pattern on ADC Data Interface (LVDS Only). ADC output is not available when this mode is

enabled. Fixed pattern = 20'b1010 1100 0101 1101 0110 (0xAC5D6).

0x0

R/W

0: Test Pattern Disabled.

1: Test Pattern Enabled.

RESERVED

Reserved. Write 0b0 to this bit.

0x0

SPI_LVDS_LANES

LVDS/SPI Lane Control. Determines the number of lanes that the ADC conversion data is clocked out on.

0x0

R/W

0: One Lane Active.

1: Multiple Lanes Active (Two for LVDS and Four for the SPI Data Interface).

RESERVED

Reserved. Write 0b0 to this bit.

0x0

DATA_INTF_MODE

Read Conversion Data Over SPI or LVDS. Acts as global LVDS enable, setting this bit to 1 powers down the

LVDS transmitters/receivers.

0x0

R/W

0: Data Read Back Over LVDS.

1: Data Read Back Over SPI Data Interface (DCS/DCLK). CLK+ is repurposed as the SPI data interface clock

(DCLK) for reading FIFO data, and CLK− is repurposed as the SPI chip select (DCS) for reading FIFO data.

AD4080BBCZ Datasheet(PDF) 84 Page - Analog Devices

AD4080BBCZ Datasheet(HTML) 84 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datasheet Download

Link URL