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AD4080BBCZ Datasheet(PDF) 6 Page - Analog Devices |
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AD4080BBCZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 95 page  Data Sheet AD4080 SPECIFICATIONS analog.com Rev. 0 | 6 of 95 TIMING SPECIFICATIONS VDD33 = 3.3 V ± 5%, VDDLDO= 1.5 V to 2.7 V, VDD11 = 1.1 V ± 5%, IOVDD = 1.1 V − 5% to 1.2 V + 5%, VREFIN = 3.0 V, fS = 40 MHz, and TA = TMIN to TMAX unless otherwise noted. Table 2. Timing Specifications Parameter Symbol Min Typ Max Unit Sampling Frequency fS 1.25 40 MHz Conversion Time tCONV 25 800 ns Acquisition Phase tACQ tCYC ns Conversion Cycle Period tCYC tCONV ns LVDS Data Interface Data Interface Clock Count N 10 Active Data Lane Count L 2 CNV± High Time tCNVH tCLK 5 × tCLK tCYC − tCNVL ns CNV± Low Time tCNVL tCLK 5 × tCLK tCYC − tCNVH ns CNV± Edge to CLK± Rising Edge Alignment tCCA 535 ps CNV± to Dx± (MSB) Ready tMSB Gain Error Correction Enabled 20.5 22.4 ns Gain Error Correction Disabled 15.7 18 ns CLK± Period tCLK 2.5 tCYC × L/N ns CLK± Frequency fCLK 1/tCLK 400 MHz CLK± to Dx± Delay tCLKD 2.1 ns CLK± to DCO± Delay (Echo Clock Mode) tDCO 2 ns DCO± to Dx± Delay (Echo Clock Mode) tDCOD 1 ns Serial Peripheral Interface (SPI) Data Interface Data Interface Clock Count, Single Conversion Result M 24 Active Data Lane Count C 1 4 Data Interface Chip Select Falling Edge (DCS) to SDOB Data Valid tDEN 5 6 ns Data Interface Clock Period (DCLK) tDCK 20 ns Data Interface Clock Low Pulse Width (DCLK) tDCKL tDCK × 0.45 ns Data Interface Clock High Pulse Width (DCLK) tDCLKH tDCK × 0.45 ns Data Interface Clock Falling Edge to Data Remains Valid Delay tDHSDO 5 ns Data Interface Clock Falling Edge to Data Valid Delay tDDSDO 9.6 ns DCLK Rising to Data Interface Chip Select Falling tDCKEN 0 ns Data Interface Chip Select High to DCLK Disabled tDCLKDIS 0 ns Data Interface Chip Select High Between Frames tDCSMIN (tDCKEN + tDCLKDIS) + 0.5 × tDCLK ns Serial Configuration Interface SCLK Period tSCK 20 ns SCLK Low Pulse Width tSCKL tSCK × 0.45 ns SCLK High Pulse Width tSCKH tSCK × 0.45 ns SCLK Falling Edge to Data Remains Valid Delay tHSDO 0.7 ns SCLK Falling Edge to Data Valid Delay tDSDO 14.5 ns CS Falling Edge to SCLK tCSSCK 0 ns Last SCLK to CS Rising tSCKCS 0 ns SDI Valid Setup Time Before SCLK Rising Edge tSSDI 1 ns SDI Valid Hold Time After SCLK Rising Edge tHSDI 0 ns SCLK Rising to Data Interface Chip Select Falling tSCKEN 0 ns |
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