MC68HC908GR4MP datasheet(222/286 Pages) FREESCALE

222 / 286 page

Serial Peripheral Interface (SPI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

222

Freescale Semiconductor

SPWOM — SPI Wired-OR Mode Bit

This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins

become open-drain outputs.

1 = Wired-OR SPSCK, MOSI, and MISO pins

0 = Normal push-pull SPSCK, MOSI, and MISO pins

SPE — SPI Enable

This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See 20.9

Resetting the SPI. Reset clears the SPE bit.

1 = SPI module enabled

0 = SPI module disabled

SPTIE— SPI Transmit Interrupt Enable

This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte

transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.

1 = SPTE CPU interrupt requests enabled

0 = SPTE CPU interrupt requests disabled

20.13.2 SPI Status and Control Register

The SPI status and control register contains flags to signal these conditions:

•

Receive data register full

•

Failure to clear SPRF bit before next byte is received (overflow error)

•

Inconsistent logic level on SS pin (mode fault error)

•

Transmit data register empty

The SPI status and control register also contains bits that perform these functions:

•

Enable error interrupts

•

Enable mode fault error detection

•

Select master SPI baud rate

SPRF — SPI Receiver Full Bit

This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data

During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register

with SPRF set and then reading the SPI data register. Reset clears the SPRF bit.

1 = Receive data register full

0 = Receive data register not full

ERRIE — Error Interrupt Enable Bit

This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears

the ERRIE bit.

1 = MODF and OVRF can generate CPU interrupt requests

0 = MODF and OVRF cannot generate CPU interrupt requests

Address: $0011

Bit 7

654321

Bit 0

Read:

SPRF

ERRIE

OVRF

MODF

SPTE

MODFEN

SPR1

SPR0

Write:

Reset:

00001000

= Unimplemented

Figure 20-14. SPI Status and Control Register (SPSCR)

MC68HC908GR4MP Datasheet(PDF) 222 Page - Freescale Semiconductor, Inc

MC68HC908GR4MP Datasheet(HTML) 222 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL