MC68HC908GR4MP datasheet(220/286 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

220

Freescale Semiconductor

20.12.3 SPSCK (Serial Clock)

The serial clock synchronizes data transmission between master and slave devices. In a master MCU,

the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex

operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.

When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data

direction register of the shared I/O port.

20.12.4 SS (Slave Select)

The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a

slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.

See 20.5 Transmission Formats. Since it is used to indicate the start of a transmission, the SS must be

toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low

between transmissions for the CPHA = 1 format. See Figure 20-12.

Figure 20-12. CPHA/SS Timing

When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as

a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can

still prevent the state of the SS from creating a MODF error. See 20.13.2 SPI Status and Control Register.

NOTE

A high voltage on the SS pin of a slave SPI puts the MISO pin in a

high-impedance state. The slave SPI ignores all incoming SPSCK clocks,

even if it was already in the middle of a transmission.

When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to

prevent multiple masters from driving MOSI and SPSCK. See 20.7.2 Mode Fault Error. For the state of

the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit

is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data

direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless

of the state of the data direction register of the shared I/O port.

The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and

reading the port data register. See Table 20-3.

Table 20-3. SPI Configuration

SPE

SPMSTR

MODFEN

SPI Configuration

State of SS Logic

X(1)

Not enabled

General-purpose I/O; SS ignored by SPI

Slave

Input-only to SPI

Master without MODF

General-purpose I/O; SS ignored by SPI

Master with MODF

Input-only to SPI

Note 1. X = Don’t care

BYTE 1

BYTE 3

MISO/MOSI

BYTE 2

MASTER SS

SLAVE SS

CPHA = 0

SLAVE SS

CPHA = 1

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