MC68HC908GR4MP datasheet(217/286 Pages) FREESCALE

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Interrupts

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

217

20.8 Interrupts

Four SPI status flags can be enabled to generate CPU interrupt requests.

Reading the SPI status and control register with SPRF set and then reading the receive data register

clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.

The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU

interrupt requests, provided that the SPI is enabled (SPE = 1).

The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt

requests, regardless of the state of the SPE bit. See Figure 20-11.

The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error

CPU interrupt request.

The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF

bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.

Figure 20-11. SPI Interrupt Request Generation

Table 20-2. SPI Interrupts

Flag

Request

SPTE

Transmitter empty

SPI transmitter CPU interrupt request

(SPTIE = 1, SPE = 1)

SPRF

Receiver full

SPI receiver CPU interrupt request

(SPRIE = 1)

OVRF

Overflow

SPI receiver/error interrupt request (ERRIE = 1)

MODF

Mode fault

SPI receiver/error interrupt request (ERRIE = 1)

SPTE

SPTIE

SPRF

SPRIE

SPE

CPU INTERRUPT REQUEST

SPI TRANSMITTER

SPI RECEIVER/ERROR

ERRIE

MODF

OVRF

MC68HC908GR4MP Datasheet(PDF) 217 Page - Freescale Semiconductor, Inc

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