MC68HC908GR4MP datasheet(216/286 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

216

Freescale Semiconductor

In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS

goes to logic 0. A mode fault in a master SPI causes the following events to occur:

•

If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.

•

The SPE bit is cleared.

•

The SPTE bit is set.

•

The SPI state counter is cleared.

•

The data direction register of the shared I/O port regains control of port drivers.

NOTE

To prevent bus contention with another master SPI after a mode fault error,

clear all SPI bits of the data direction register of the shared I/O port before

enabling the SPI.

When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission.

When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes

back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins

when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK

returns to its idle level following the shift of the last data bit. See 20.5 Transmission Formats.

NOTE

Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit

has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows

the difference between a MODF occurring when the SPI is a master and

when it is a slave.

When CPHA = 0, a MODF occurs if a slave is selected (SS is low) and later

unselected (SS is high) even if no SPSCK is sent to that slave. This

happens because SS low indicates the start of the transmission (MISO

driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave

can be selected and then later unselected with no transmission occurring.

Therefore, MODF does not occur since a transmission was never begun.

In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the

ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort

the SPI transmission by clearing the SPE bit of the slave.

NOTE

A high on the SS pin of a slave SPI puts the MISO pin in a high impedance

state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was

already in the middle of a transmission.

To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This

entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.

MC68HC908GR4MP Datasheet(PDF) 216 Page - Freescale Semiconductor, Inc

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