MC68HC908GR4MP datasheet(252/286 Pages) FREESCALE

252 / 286 page

Electrical Specifications

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

252

Freescale Semiconductor

Pullup resistors (as input only)

Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0,

PTD6/T2CH0–PTD0/SS

RPU

Capacitance

Ports (as input or output)

COut

CIn

—

Monitor mode entry voltage

VTST

VDD +2.5

—

VDD +4.0

Low-voltage inhibit, trip falling voltage – target

VTRIPF

2.35

2.60

2.70

Low-voltage inhibit, trip rising voltage – target

VTRIPR

2.45

2.66

2.80

Low-voltage inhibit reset/recover hysteresis – target

(VTRIPF + VHYS = VTRIPR)

VHYS

—60

—

Input hysteresis (alternative input functions only)(7), (12)

VInHYS

0.06 x VDD

——

POR rearm voltage(7), (13)

VPOR

—

100

POR reset voltage(14)

VPORRST

700

800

POR rise time ramp rate(7), (15)

RPOR

0.035

—

V/ms

1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

2. Typical values reflect average measurements at midpoint of voltage range, 25

°C only.

3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No

dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly

affects run IDD. Measured with all modules enabled.

4. Wait IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less

than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait

IDD. Measured with PLL and LVI enabled.

5. Stop IDD is measured with OSC1 = VSS.

6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V

from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs.

7. This parameter is characterized and not tested on each device.

8. All functional non-supply pins are internally clamped to VSS and VDD.

9. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values for positive and negative clamp voltages, then use the larger of the two values.

10. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current

conditions. If positive injection current (VIN > VDD) is greater than IDD, the injection current may flow out of VDD and could

result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is

present, or if clock rate is very low (which would reduce overall power consumption).

11. Pullups and pulldowns are disabled.

12. Digital inputs have hysteresis whenever they are configured for any alternative peripheral input function other than as a

general-purpose input.

13. Maximum is highest voltage that POR is guaranteed.

14. Maximum is highest voltage that POR is possible.

15. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum

VDD is reached.

Characteristic(1)

Symbol

Min

Typ(2)

Max

Unit

MC68HC908GR4MP Datasheet(PDF) 252 Page - Freescale Semiconductor, Inc

MC68HC908GR4MP Datasheet(HTML) 252 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL