MC68HC908GR4MP datasheet(253/286 Pages) FREESCALE

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5.0 V Control Timing

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

253

23.6 5.0 V Control Timing

Characteristic(1)

1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VSS unless otherwise noted.

Symbol

Min

Max

Unit

Frequency of operation(2)

Crystal option

External clock option(3)

2. See 23.8 Clock Generation Module Characteristics for more information.

3. No more than 10% duty cycle deviation from 50%

fosc

dc(4)

4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this

information.

100

32.8

kHz

MHz

Internal operating frequency

fop

—8.2

MHz

Internal clock period (1/fOP)tcyc

122

—

RST input pulse width low(5)

5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

tIRL

—

IRQ interrupt pulse width low(6)

(edge-triggered)

6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.

tILIH

—

IRQ interrupt pulse period

tILIL

Note 8

—

tcyc

16-bit timer(7)

Input capture pulse width

Input capture period

7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.

8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to execute the interrupt service

routine plus tcyc.

tTH,tTL

tTLTL

Note 8

—

tcyc

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