MC68HC908GR4MP datasheet(112/286 Pages) FREESCALE

112 / 286 page

Flash Memory

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

112

Freescale Semiconductor

Set the PGM bit. This configures the memory for program operation and enables the latching of

address and data for programming.

Read from the FLASH block protect register.

Write any data to any FLASH address within the row address range desired.

Wait for a time, tnvs (min. 10μs).

Set the HVEN bit.

Wait for a time, tpgs (min. 5μs).

Write data to the FLASH address to be programmed.

Wait for a time, tPROG (min. 30μs).

Repeat step 7 and 8 until all the bytes within the row are programmed.

10.

Clear the PGM bit.*

11.

Wait for a time, tnvh (min. 5μs).

12.

Clear the HVEN bit.

13.

After time, trcv (typical 1μs), the memory can be accessed in read mode again.

This program sequence is repeated throughout the memory until all data is programmed.

NOTE

Programming and erasing of FLASH locations cannot be performed by

code being executed from the FLASH memory. While these operations

must be performed in the order shown, other unrelated operations may

occur between the steps. Care must be taken within the FLASH array

memory space such as the COP control register (COPCTL) at $FFFF.

NOTE

It is highly recommended that interrupts be disabled during program/erase

operations.

NOTE

Do not exceed tPROG maximum or tHV maximum. tHV is defined as the

cumulative high voltage programming time to the same row before next

erase. tHV must satisfy this condition:

tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum

Refer to 23.16 Memory Characteristics.

NOTE

The time between programming the FLASH address change (step 7 to

step 7), or the time between the last FLASH programmed to clearing the

PGM bit (step 7 to step 10) must not exceed the maximum programming

time, tPROG maximum.

CAUTION

Be cautious when programming the FLASH array to ensure that

non-FLASH locations are not used as the address that is written to when

selecting either the desired row address range in step 3 of the algorithm or

the byte to be programmed in step 7 of the algorithm. This applies

particularly to $FFD4–$FFDF.

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