MC68HC908GR4MP datasheet(127/286 Pages) FREESCALE

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MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

127

Chapter 14

Low-Voltage Inhibit (LVI)

14.1 Introduction

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin

and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.

14.2 Features

Features of the LVI module include:

•

Programmable LVI reset

•

Selectable LVI trip voltage

•

Programmable stop mode operation

14.3 Functional Description

Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module

contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD,

enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI

module to generate a reset when VDD falls below the trip point voltage, VTRIPF. Setting the LVI enable in

stop mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5V or 3V trip point bit,

LVI5OR3, enables VTRIPF to be configured for 5V operation. Clearing the LVI5OR3 bit enables VTRIPF to

be configured for 3V operation. The actual trip points are shown in Chapter 23 Electrical Specifications.

NOTE

After a power-on reset (POR) the LVI’s default mode of operation is 3 V. If

a 5V system is used, the user must set the LVI5OR3 bit to raise the trip

point to 5V operation. Note that this must be done after every POR since

the default will revert back to 3V mode after each POR. If the VDD supply is

below the 5V mode trip voltage but above the 3V mode trip voltage when

POR is released, the part will operate because VTRIPF defaults to 3V mode

after a POR. So, in a 5V system care must be taken to ensure that VDD is

above the 5V mode trip voltage after POR is released.

If the user requires 5V mode and sets the LVI5OR3 bit after a POR while

the VDD supply is not above the VTRIPR for 5V mode, the MCU will

immediately go into reset. The LVI in this case will hold the part in reset until

either VDD goes above the rising 5V trip point, VTRIPR, which will release

reset or VDD decreases to approximately 0 V which will re-trigger the POR

and reset the trip point to 3V operation.

MC68HC908GR4MP Datasheet(PDF) 127 Page - Freescale Semiconductor, Inc