MC68HC908GR4MP datasheet(183/286 Pages) FREESCALE

183 / 286 page

I/O Registers

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

183

RPF — Reception in Progress Flag Bit

This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search.

RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits

(usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling

RPF before disabling the SCI module or entering stop mode can show whether a reception is in

progress.

1 = Reception in progress

0 = No reception in progress

18.8.6 SCI Data Register

The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit

shift registers. Reset has no effect on data in the SCI data register.

R7/T7–R0/T0 — Receive/Transmit Data Bits

Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018

writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.

NOTE

Do not use read/modify/write instructions on the SCI data register.

18.8.7 SCI Baud Rate Register

The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.

Address:

$0018

Bit 7

654321

Bit 0

Read:

R7R6R5

R4R3R2

Write:

Reset:

Unaffected by reset

Figure 18-15. SCI Data Register (SCDR)

Address:

$0019

Bit 7

654321

Bit 0

Read:

SCP1

SCP0

SCR2

SCR1

SCR0

Write:

Reset:

00000000

= Unimplemented

= Reserved

Figure 18-16. SCI Baud Rate Register (SCBR)

MC68HC908GR4MP Datasheet(PDF) 183 Page - Freescale Semiconductor, Inc

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