MC68HC908GR4MP datasheet(181/286 Pages) FREESCALE

181 / 286 page

I/O Registers

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

181

IDLE — Receiver Idle Bit

This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.

IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE

bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must

receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after

the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition

can set the IDLE bit. Reset clears the IDLE bit.

1 = Receiver input idle

0 = Receiver input active (or idle since the IDLE bit was cleared)

OR — Receiver Overrun Bit

This clearable, read-only bit is set when software fails to read the SCDR before the receive shift

ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is

not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears

the OR bit.

1 = Receive shift register full and SCRF = 1

0 = No receiver overrun

Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing

sequence. Figure 18-13 shows the normal flag-clearing sequence and an example of an overrun

caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit

because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next

flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.

In applications that are subject to software latency or in which it is important to know which byte is lost

due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after

reading the data register.

NF — Receiver Noise Flag Bit

This clearable, read-only bit is set when the SCI detects noise on the PE1/RxD pin. NF generates an

NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and

then reading the SCDR. Reset clears the NF bit.

1 = Noise detected

0 = No noise detected

FE — Receiver Framing Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error

CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set

and then reading the SCDR. Reset clears the FE bit.

1 = Framing error detected

0 = No framing error detected

PE — Receiver Parity Error Bit

This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates

a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with

PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

MC68HC908GR4MP Datasheet(PDF) 181 Page - Freescale Semiconductor, Inc

MC68HC908GR4MP Datasheet(HTML) 181 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL